ED DDR3 1G PCH9000 Samsung Semiconductor, ED DDR3 1G PCH9000 Datasheet - Page 40

• Manufacturer Part Number: ED DDR3 1G PCH9000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCH9000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 160mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
[ Table 41 ] Input/Output Capacitance
Note :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
ANALYZER( VNA)") with V
V
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
DD
=V
DDQ
=1.5V, V
Parameter
BIAS
=V
DD
DD
/2 and on-die termination off.
, V
DDQ
, V
CDI_ADD_CMD
SS
CDI_CTRL
Symbol
CDDQS
, V
CDCK
CDIO
CCK
CZQ
CIO
CI
SSQ
applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary).
0.75
Min
-0.5
-0.5
-0.5
1.5
0.8
0
0
DDR3-800
-
Page 40 of 61
Max
0.15
0.2
0.5
3.0
1.6
1.5
0.3
0.3
3
0.75
Min
-0.5
-0.5
-0.5
1.5
0.8
DDR3-1066
0
0
-
Max
0.15
2.7
1.6
1.5
0.2
0.3
0.5
0.3
3
0.75
Min
-0.4
-0.4
-0.5
1.5
0.8
DDR3-1333
0
0
-
Max
0.15
0.15
2.5
1.4
1.3
0.2
0.4
0.3
3
1Gb DDR3 SDRAM
Rev. 1.0 February 2009
0.75
Min
-0.4
-0.4
-0.5
1.5
0.8
DDR3-1600
0
0
-
Max
0.15
0.15
2.3
1.4
1.3
0.2
0.4
0.3
3
Units
pF
pF
pF
pF
pF
pF
pF
pF
pF
2,3,9,10
2, 3, 12
2,3,7,8
Notes
2,3,11
1,2,3
2,3,4
2,3,6
2,3,5
2,3