IS43DR16640A-25DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16640A-25DBLI Datasheet - Page 19

• Manufacturer Part Number: IS43DR16640A-25DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16640A-25DBLI

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR81280A, IS43/46DR16640A
IDD Specifications and Conditions
IDD Measurement Conditions
Notes:
1.
2.
3.
4.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00D, 8/17/2010
Symbol Parameter/Condition
IDD3Ps
IDD3Pf
IDD4W
IDD2Q
IDD2N
IDD3N
IDD5D
IDD2P
IDD4R
IDD5B
IDD0
IDD1
IDD6
IDD7
Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#. IDD values must be met with all combinations of EMRS bits 10 and 11.
For DDR2‐667/800 testing, tCK in the Conditions should be interpreted as tCK(avg).
Definitions for IDD:
Legend: A=Activate, RA=Read with Auto‐Precharge, D=DESELECT.
Operating Current ‐ One bank Active ‐ Precharge:
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
Operating Current ‐ One bank Active ‐ Read ‐ Precharge:
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge Power‐Down Current:
Precharge Standby Current:
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge Quiet Standby Current:
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active Power‐Down Current:
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
“0”(Fast Power‐down Exit).
Active Power‐Down Current:
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
“1”(Slow Power‐down Exit).
Active Standby Current:
All banks open;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
Operating Current ‐ Burst Read:
All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating Current ‐ Burst Write:
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst Auto‐Refresh Current:
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Refresh Current:
tCK = tCK(IDD); Refresh command frequency satisfying tREFI; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Self‐Refresh Current:
CK and CK# at 0 V; CKE 0.2 V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating Bank Interleave Read Current:
1.
a.
b.
c.
d.
e.
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) ‐ 1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW =
tFAW(IDD), tRCD = 1 x tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R;
LOW is defined as VIN ≤ VILAC(max).
HIGH is defined as VIN ≥ VIHAC(min).
STABLE = inputs stable at a HIGH or LOW level.
FLOATING = inputs at VREF = VDDQ/2.
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs
changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
.
. MRS A12 bit is set to
. MRS A12 bit is set to
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