IS43DR16640A-25DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16640A-25DBLI Datasheet - Page 8

• Manufacturer Part Number: IS43DR16640A-25DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16640A-25DBLI

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR81280A, IS43/46DR16640A
contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in
precharge state.
Extended Mode Register 2 (EMR[2]) Diagram
Notes:
1.
2.
3.
DDR2 Extended Mode Register 3 (EMR[3]) Setting
No function is defined in extended mode register 3. The default value of the extended mode register 3 is not defined. Therefore, the
extended mode register 3 must be programmed during initialization for proper operation.
DDR2 Extended Mode Register 3 (EMR[3]) Diagram
Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3].
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00D, 8/17/2010
Address
A13
A12
A11
A10
A3‐A6, and A8‐A13 are reserved for future use and must be set to 0 when programming the EMR[2].
Only Industrial and Automotive grade devices support the high temperature Self‐Refresh Mode. The controller can set the EMR (2) [A7] bit to enable this self‐
refresh rate if Tc > 85°C while in self‐refresh operation. TOPER may not be violated.
If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data
integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
Field
A9
A8
A6
A5
A4
A3
BA2
BA1
BA0
A7
A2
A1
A0
Mode Register
Address Field
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Register
PASR
Mode
SRFt
0
1
0
0
0
0
0
0
0
0
0
0
0
(3)
BA2
0*
BA1
1
BA0
1
A7
A2
0
1
0
0
0
0
1
1
1
1
A13
0*
A12
0*
A1
0
0
1
1
0
0
1
1
High Temperature Self-Refresh Rate Enable
A11
0*
A10
0*
A0
0
1
0
1
0
1
0
1
A9
0*
Enable
Disable
Partial Array Self Refresh for 8
A8
(2)
0*
Quarter Array
Quarter array
Half Array
Full Array
Half array
A7
1/8 array
3/4 array
1/8 array
0*
Banks
A6
0*
A5
0*
A4
0*
010, 011, 100, 101, 110, 111
000, 001, 010, 011
100, 101, 110, 111
All combinations
A3
0*
000, 001
110, 111
BA[2:0]
000
111
A2
0*
A1
0*
8
A0
0*