MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 48

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1–5, 14-17, 33; notes appear on pages 50–53) (0°C ≤ T
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
DQS-DQ skew, first DQS to last DQ valid, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
CL = 2.5
CL = 2
(continued on following page)
SYMBOL
t
t
t
t
DQSQA
CK(2.5)
DQSCK
t
t
t
t
t
t
t
DQSH
DQSQ
t
DIPW
DQSL
DQSS
t
CK(2)
t
t
t
t
t
t
t
t
RPRE
RPST
MRD
t
t
t
t
t
QHS
t
t
t
DSH
t
t
t
IPW
RAS
RAP
RCD
RRD
t
DSS
t
t
RFC
t
DH
QH
AC
CH
DS
HP
HZ
IH
IH
IH
RC
CL
LZ
IS
RP
F
F
S
S
48
t
-
CH,
-0.75
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
t
7.5
0.5
0.5
0.2
0.2
.90
.90
2.2
t
0.9
0.4
QHS
15
HP
45
15
60
67
15
15
7
1
1
2
t
CL
A
-7
≤ +70°C; V
120,000
+0.75
+0.75
+0.75
+0.75
MAX
0.55
0.55
1.25
0.75
0.5
0.7
1.1
0.6
12
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
-
CH,
-0.75
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
t
7.5
0.5
0.5
0.2
0.2
.90
.90
2.2
t
0.9
0.4
10
15
QHS
45
20
65
75
20
20
DD
HP
1
1
2
t
CL
Q = +2.5V ±0.2V, V
-75
120,000
+0.75
+0.75
+0.75
+0.75
MAX
0.55
0.55
1.25
0.75
0.5
0.7
1.1
0.6
512Mb: x4, x8, x16
12
12
t
-
CH,
MIN
0.45
0.45
0.35
0.35
0.75
-0.8
-0.8
-0.8
-0.8
t
t
0.6
0.6
0.2
0.2
1.1
1.1
1.1
1.1
2.5
0.9
0.4
QHS
10
16
50
20
70
80
20
20
HP
8
2
2
t
CL
DDR SDRAM
-8
120,000
MAX
+0.8
0.55
0.55
+0.8
1.25
+0.8
+0.8
DD
0.6
0.8
1.1
0.6
12
12
1
= +2.5V ±0.2V)
©2000, Micron Technology, Inc.
ADVANCE
UNITS NOTES
t
t
t
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
ns
25, 26,
26, 31
26, 31
25, 26
30
30
52
52
31
36
34
18
18
14
14
14
14
34
35
50
42