MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 58

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
DQS, or LDQS/UDQS
All DQs collectively
DQ (Last data valid)
DQ (First data valid)
NOTE: 1. t DSH
CK#
DQS
CK
CK#
DM
DQ
3
2
CK
2. t DSS
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
NOTE: 1. t DQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.
T0
7
2. DQs transitioning after DQS transition define t DQSQ window.
3. All DQs must transition by t DQSQ after DQS transitions, regardless of t AC.
4. t AC is the DQ output window relative to CK, and is the“long term” component of DQ skew.
5. t LZ
6. t LZ
7. READ command with CL = 2 issued at T0.
(MIN)
t LZ
(MIN)
t LZ
T0
(MAX)
(MIN)
Data Output Timing -
(MIN)
(MAX)
t DQSS
3
generally occurs during t DQSS
generally occurs during t DQSS
t WPRES
, t AC
T1
, t AC
(MIN)
(MAX)
t DS
t RPRE
t LZ
, and t HZ
t WPRE
, and t HZ
(MIN)
Data Input Timing
T1
DI
b
T2
t DSH 1
(MIN)
Figure 28
Figure 29
(MAX)
t DQSCK
t DQSCK
t DH
T2
T2
T2
t LZ
are the first valid signal transition.
T1n
58
are the latest valid signal transition.
(MAX)
T2n
t DQSL
1
1
t DSS 2
(MAX)
(MIN)
T2n
T2n
T2n
t
AC and
t AC
T2
(MAX)
(MIN)
T3
4
t DQSH t WPST
(MIN)
t DSH 1
T3
T3
T3
.
.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
T2n
t
DQSCK
t DSS 2
T3n
T3n
T3n
t AC
TRANSITIONING DATA
DON’T CARE
4
T4
(MAX)
T3
512Mb: x4, x8, x16
T4
T4
T4
T4n
t DQSCK
t DQSCK
T4n
T4n
T4n
DDR SDRAM
T5
1
1
(MAX)
(MIN)
T5
T5
T5
©2000, Micron Technology, Inc.
t HZ
t HZ
T5n
ADVANCE
t HZ
t HZ
(MAX)
(MIN)
t RPST
(MAX)
T5n
(MIN)
T5n
T5n
T6