MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 60

• Manufacturer Part Number: MT46V32M16D2TH-7L
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16D2TH-7L

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

TIMING PARAMETERS
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
A0-A9, A11, A12
SYMBOL
t
t
t
t
t
CH
CL
CK (2.5)
CK (2)
IH
COMMAND
BA0, BA1
V
DQS
CK#
CKE
A10
V
DD
V
DM
V
DQ
CK
TT
REF
DD
NOTE: 1. V
Q
1
6
LVCMOS
LOW LEVEL
MIN
0.45
0.45
7.5
7
1
t
VTD
2. Although not required by the Micron device, JEDEC specifies resetting the DLL with A8 = H.
3. t MRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied after the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command,
-7
V
V
RA = Row Address, Bank Address
1
TT
DD
DD
MAX
0.55
0.55
12
12
Q, V
/V
is not applied directly to the device; however, t VTD should be greater than or equal to zero to avoid device latch-up. V
DD
Power-up:
V
CK stable
DD
TT
Q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the V
and
and V
MIN
0.45
0.45
7.5
10
1
T = 200µs
-75
REF
(
(
(
(
(
(
(
(
(
MAX
(
)
)
(
)
(
)
(
)
(
)
(
)
)
)
must be equal to or less than V
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
)
)
)
(
)
(
)
)
)
)
0.55
0.55
(
(
(
(
)
)
)
)
)
)
12
INITIALIZE AND LOAD MODE REGISTERS
2
t IS
t
MIN
IS
0.45
0.45
1.1
NOP
T0
10
8
High-Z
High-Z
t IH
t
t
IH
CH
t
-8
CK
MAX
0.55
0.55
12
12
t
CL
ALL BANKS
t IS
PRE
T1
UNITS
t IH
t
t
ns
ns
ns
CK
CK
DD
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
t RP
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
Load Extended
(
(
(
(
(
(
)
)
Mode Register
)
)
)
)
)
)
)
+ 0.3V. Alternatively, V
60
t IS
t IS
t IS
BA0 = H,
BA1 = L
CODE
CODE
LMR
T2
t IH
t IH
t IH
t MRD
SYMBOL
t
t
t
t
t
IS
MRD
RFC
RP
VTD
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
Load Mode
Register
BA0 = L,
BA1 = L
CODE
CODE
Ta0
LMR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
t MRD
TT
MIN
15
67
15
1
0
(
(
(
(
(
(
(
may be 1.35V maximum during power up, even if
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
ALL BANKS
-7
t
IS
MAX
Tb0
PRE
200 cycles of CK
t
IH
t RP
512Mb: x4, x8, x16
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
(
)
)
)
)
)
)
)
)
MIN
75
20
TT
15
1
0
supply and the input pin.
-75
Tc0
3
AR
MAX
t RFC
DDR SDRAM
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
(
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
(
)
)
)
)
)
)
)
)
MIN
1.1
80
20
16
Td0
0
AR
©2000, Micron Technology, Inc.
-8
ADVANCE
t RFC
MAX
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
(
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
(
)
DD
5
Q
DON’T CARE
,
ACT 5
Te0
RA
RA
BA
UNITS
ns
ns
ns
ns
ns