LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 27

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Datasheet
Figure 4. Flash Buffer Read Cycle
5.2.1.1.2 Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow and the 82551ER issues a target-disconnect at
the first data access. The 82551ER asserts the STOP# signal to indicate a target-disconnect. The
figures below illustrate memory CPU read and write accesses to the 128 KB Flash buffer. The
longest burst cycle to the Flash buffer contains one data access only.
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551ER controls
the TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from
the Flash buffer. When TRDY# is asserted, the 82551ER drives valid data on the AD[31:0] lines.
The CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read
accesses can be byte or word length.
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
MEM RD
ADDR
BE#
Networking Silicon — 82551ER
DATA
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