LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 56

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

82551ER — Networking Silicon
7.1.12
7.1.13
7.1.14
48
Table 16. ID Fields Programming
The 82551ER provides support for configurable Subsystem Vendor ID and Subsystem ID fields.
After hardware reset is de-asserted, the 82551ER automatically reads addresses Ah through Ch of
the EEPROM. The first of these 16-bit values is used for controlling various 82551ER functions.
The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the
default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively.
The 82551ER checks bit numbers 15, 14, and 13 in the EEPROM, word Ah and functions are listed
in
a. The Revision ID is subject to change according to the silicon stepping.
b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.
The above table implies that if the 82551ER detects the presence of an EEPROM (as indicated by a
value of 1b in bits 15 and 14), then bit number 13 determines whether the values read from the
EEPROM, words Bh and Ch, are loaded into the Subsystem ID (word Bh) and Subsystem Vendor
ID (word Ch) fields. If bits 15 and 14 equal 1b and bit 13 equals 1b, the three least significant bits
of the Revision ID field are programmed by bits 10:8 of the first EEPROM word, Ah.
Between the de-assertion of reset and the completion of the automatic EEPROM read, the
82551ER does not respond to any PCI configuration cycles. If the 82551ER happens to be accessed
during this time, it will Retry the access. More information on Retry is provided in
5.2.1.1.3, “Retry Premature
Capability Pointer
The Capability Pointer is a hard-coded byte register with a value of DCh. It provides an offset
within the Configuration Space for the location of the Power Management registers.
Interrupt Line Register
The Interrupt Line register identifies which system interrupt request line on the interrupt controller
the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.
Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins,
INTA# through INTD#, a PCI device is connected to. The 82551ER is connected the INTA# pin.
11b
00b
01b
01b
01b
(Bits 15:14)
Signature
Table
b
, 10b,
16.
X
1b
0b
0b
(Bit 13)
ID
X
0b
0b
X
(Bit 7)
AltID
Accesses”.
1209h
1209h
1209h
1209h
Device
ID
Vendor
8086h
8086h
8086h
8086h
ID
0Fh
Word Ah, bits
10:8
0Fh
08h
(A-0 and A-1)
Revision ID
a
0000h
Word Bh
Word Bh
Word Bh
Subsystem
ID
0000h
Word Ch
Word Ch
Word Ch
Subsystem
Vendor ID
Section
Datasheet