MT48H8M16LFB4-75 IT:J TR Micron Technology Inc, MT48H8M16LFB4-75 IT:J TR Datasheet
MT48H8M16LFB4-75 IT:J TR
Specifications of MT48H8M16LFB4-75 IT:J TR
Related parts for MT48H8M16LFB4-75 IT:J TR
MT48H8M16LFB4-75 IT:J TR Summary of contents
Page 1
... PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__1.fm - Rev. E 4/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Options • Vdd/Vddq – 1.8V/1.8V • Addressing – Standard addressing option • Configuration – 8 Meg Meg banks) – ...
Page 2
... Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Revision History: Commands, Operations, and Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35mTOC.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2008 Micron Technology, Inc. All rights reserved. ...
Page 3
... Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Figure 52: Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35mLOF.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2008 Micron Technology, Inc. All rights reserved. ...
Page 4
... Truth Table – CKE .34 Table 19: Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35mLOT.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2008 Micron Technology, Inc. All rights reserved. ...
Page 5
... General Description The 128Mb Mobile SDRAM is a high-speed CMOS, dynamic random access memory containing 134,217,728 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits. Each of the x32’ ...
Page 6
... WE# CAS# RAS# EXT mode register Refresh counter Mode register Address Address BA0, BA1 register PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Bank 0 Row Row address Bank 0 address MUX memory latch and decoder Sense amplifiers I/O gating ...
Page 7
... CAS# RAS# EXT mode register Refresh counter Mode register Address Address BA0, BA1 register PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Bank 0 Row- row- address address memory MUX latch and decode Sense amplifiers I/O gating ...
Page 8
... Ball Assignments Figure 4: 54-Ball VFBGA (Top View Notes: 1. The E2 pin must be connected to Vss, Vssq, or left floating. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Vss DQ15 Vssq Vddq DQ14 DQ13 DQ12 DQ11 Vssq Vddq DQ10 DQ9 ...
Page 9
... Figure 5: 90-Ball VFBGA (Top View Notes: 1. The K2 pin must be connected to Vss, Vssq, or left floating. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM DQ26 DQ24 V SS DQ28 Vddq Vssq Vssq DQ27 DQ25 Vssq DQ29 DQ30 Vddq DQ31 NC ...
Page 10
... Meg x 16, 4 Meg x 32 Mobile SDRAM Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...
Page 11
... A3, F1, L3 E3, E7, H3, H7, K3 PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Symbol Type Vddq Supply DQ power: Provides isolated power to DQ for improved noise immunity. Vssq Supply DQ ground: Provides isolated ground to DQ for improved noise immunity. ...
Page 12
... SMD ball pads. 3.2 6.4 0.8 TYP Exposed plated 3.2 features in all corners are floating nonbiased metal. Notes: 1. All dimensions are in millimeters. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM 0.65 ±0.05 8 ±0.1 4 ±0.05 Ball ±0. ± ...
Page 13
... Pre-reflow balls are Ø0. Ø0.4 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 6.4 Notes: 1. All dimensions are in millimeters. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM 0.65 ±0.05 4 ±0.05 Ball ±0.1 H ...
Page 14
... Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance: DQ Notes: 1. This parameter is sampled. Vdd, Vddq = +1.8V MHz. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Electrical Specifications Symbol Min Vdd/Vddq –0.35 Vin –0.35 T – ...
Page 15
... No accesses in progress Operating current: Burst mode; READ or WRITE; All banks active; Half of DQ toggling every cycle Auto refresh current: CKE = HIGH; CS# = HIGH Deep power-down PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Symbol Idd1 (MIN) Idd2P Idd2N ...
Page 16
... Enables on-die refresh and address counters. 10. Values for Idd7 85°C full array and partial array are guaranteed for the entire temperature range. All other Idd7 values are estimated. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Symbol I Full array, 85°C I Full array, 45° ...
Page 17
... PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM –20 – Temperature (°C) 17 Electrical Specifications Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 18
... Refresh period (8192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH-to-ACTIVE command PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM -6 Symbol Min Max – 5 ...
Page 19
... HZ defines the time at which the output achieves the open circuit condition not a ref- erence to Voh or Vol. The last valid data element will meet 8. The 128Mb Mobile SDRAM requires 4096 AUTO REFRESH cycles every 64ms ( a distributed AUTO REFRESH command every 15.6µs meets the refresh requirement and ensures that each row is refreshed ...
Page 20
... The full variation in drive current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM t CKS. Clock(s) specified as a reference only at minimum cycle rate. t ...
Page 21
... The full variation in drive current from minimum to maximum, due to process, voltage, and temperature, will lie within the outer bounding lines of the I-V curves. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Pull-Down Current (mA) Min Max 0.00 ...
Page 22
... I-V curves. 3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive strength. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Pull-Down Current (mA) Min Max 0.00 ...
Page 23
... Changed to Preliminary status Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/08 • Initial release PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac 128mb_mobile_sdram_y35m_rev_hist__5.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Revision History: Device Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 ©2008 Micron Technology, Inc. All rights reserved. ...
Page 24
... Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random- access operation. Mobile SDRAM is designed to operate in 1.8V memory systems. An auto refresh mode is provided, along with power-saving, power-down, and deep power-down modes. All inputs and outputs are LVTTL-compatible. ...
Page 25
... Internal refresh counter controls row addressing; all inputs and I/Os are for CKE. 9. A[11:0] define the op-code written to the mode register. 10. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay). PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CS# RAS# CAS# WE ...
Page 26
... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to a selected SDRAM (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...
Page 27
... LOW, the corresponding data is written to memory; if the DQM signal is registered HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that byte/column location. Figure 11 shows the WRITE command. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK CKE HIGH CS# ...
Page 28
... Care.” After a bank has been precharged the idle state and must be acti- vated prior to any READ or WRITE commands being issued to that bank. Figure 12 on page 29 shows the PRECHARGE command. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM HIGH CS# Column address EN AP ...
Page 29
... SELF REFRESH The SELF REFRESH command is used to place the device in self refresh mode. The self refresh mode is used to retain data in the SDRAM while the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. ...
Page 30
... The states listed below must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or supported commands to the other bank should be issued on any clock edge occurring during these states. Supported commands to any PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM RAS# CAS# WE ...
Page 31
... READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Starts with registration of a PRECHARGE command and ends when met ...
Page 32
... AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands can only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM RAS# CAS# WE# Command/Action ...
Page 33
... The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM met, where WR begins when the WRITE to bank m is reg- Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 34
... H H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND of COMMAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all-banks-idle state in time for clock edge (provided that 6 ...
Page 35
... When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register powers unknown state, it should be loaded prior to issuing any operational command. The low-power SDRAM initialization sequence is shown in Figure 13 ...
Page 36
... There are two mode registers in the Mobile SDRAM component, the mode register and the extended mode register (EMR). The mode register is illustrated in Figure 14 on page 37. The mode register defines the specific mode of operation of the Mobile SDRAM, including burst length (BL), burst type, CAS latency (CL), operating mode, and write burst mode ...
Page 37
... Burst Length (BL) Read and write accesses to the SDRAM are burst oriented and the BL is programmable, (see Figure 14). The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths contin- uous locations are available for both the sequential and the interleaved burst types, and a continuous page burst is available for the sequential type ...
Page 38
... DQ start driving after T1 and the data is valid by T2, as shown in Figure 15 on page 39. Reserved states should not be used as unknown operation or incompatibility with future versions may result. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Order of Accesses Within a Burst Type = Sequential A0 0 0-1 ...
Page 39
... Extended Mode Register (EMR) The EMR controls additional functions beyond those controlled by the mode register. These additional functions are special features of the Mobile SDRAM device that help reduce overall system power consumption and include TCSR, PASR, and output drive strength. ...
Page 40
... Temperature-Compensated Self Refresh (TCSR) Mobile SDRAM includes a temperature sensor that is implemented for automatic control of the self refresh oscillator on the device. Programming the TCSR bits has no effect on the device. The self refresh oscillator will continue refresh at the optimal factory-programmed rate for the device temperature ...
Page 41
... Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, that selects both the bank and the row to be activated (see Figure 17). ...
Page 42
... This is shown in Figure 19 on page 44 for CL2 and CL3. Mobile SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command ...
Page 43
... Figure 18: Consecutive READ Bursts Command Address Command Address Notes: 1. Each READ command can be to any bank. DQM is LOW. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK READ NOP NOP Bank, Col n Dout CLK READ NOP ...
Page 44
... READ burst, provided that I/O contention can be avoided given system design, there is a possibility that the device driving the input data will go Low-Z before the SDRAM High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
Page 45
... Command Address DQ Notes The READ command can be to any bank, and the WRITE command can be to any bank burst of one is used, DQM is not required. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ NOP NOP NOP ...
Page 46
... The READ command can be to any bank, and the WRITE command can be to any bank. Figure 22: READ-to-PRECHARGE Command Address Command Address Notes: 1. DQM is LOW. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK READ NOP NOP Bank, Col n DQ Transitioning data ...
Page 47
... This is shown in Figure 23 for each possible CL; data element the last desired data element of a longer burst. Figure 23: Terminating a READ Burst Command Address Command Address Notes: 1. DQM is LOW. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK READ NOP NOP Bank, Col n Dout DQ ...
Page 48
... Enable auto precharge Row A10 BA0, BA1 Bank RCD - bank 0 t RAS - bank bank 0 t RRD Notes: 1. For this example and PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ NOP ACTIVE t CMH Row Column m Row Bank 0 Bank ...
Page 49
... Row Column A10 Row BA0, BA1 Bank Bank DQ t RCD Notes: 1. For this example PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM NOP NOP NOP t CMH Dout Dout m m All locations within same row CAS latency Full-page burst does not self-terminate ...
Page 50
... Row Address Enable auto precharge A10 Row Disable auto precharge BA0, BA1 Bank DQ t RCD Notes: 1. For this example and PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ NOP NOP t CMH Column m Bank Dout Timing Diagrams ...
Page 51
... WRITE command, and the data provided coincident with the new command applies to the new command (seeFigure 28 on page 52). Data either the last of a burst of two or the last desired data element of a longer burst. Mobile SDRAM uses a pipelined archi- tecture and therefore does not require the 2n rule associated with a prefetch architec- ture ...
Page 52
... PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length bursts or continuous page bursts. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK WRITE ...
Page 53
... WRITE-to-READ Command Address Notes: 1. The WRITE command can be to any bank, and the READ command can be to any bank. DQM is LOW for illustration. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK WRITE WRITE WRITE Bank, ...
Page 54
... BURST TERMINATE command. This is shown in Figure 32 on page 55, where data n is the last desired data element of a longer burst. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK ...
Page 55
... AH BA0, BA1 Bank 0 Bank Din RCD - bank 0 t RAS - bank bank 0 t RRD Notes: 1. For this example PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK BURST NEXT WRITE TERMINATE COMMAND Bank, Address Col n Din DQ ...
Page 56
... Address Row Row A10 BA0, BA1 Bank DQ t RCD t Notes must be satisfied prior to issuing a PRECHARGE command. 2. Page left open; no PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMH t CMS Column m Bank Din m Din ...
Page 57
... Auto precharge is a feature that performs the same individual-bank PRECHARGE func- tion described previously, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM ...
Page 58
... WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is registered (see Figure 37 on page 59). PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM t RP) is completed. This is determined explicit PRECHARGE command was t RAS lock-out ...
Page 59
... Page Bank n active Internal States Bank m Address 1 DQM DQ Notes: 1. DQM is HIGH prevent D PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ - AP READ - AP NOP NOP Bank n Bank m Page active READ with burst of 4 Interrupt burst, precharge Page active ...
Page 60
... Row Address Enable auto precharge Row A10 BA0, BA1 Bank DQ t RCD t RAS t RC Notes: 1. For this example and PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ NOP NOP t CMH Column m Bank Dout Timing Diagrams ...
Page 61
... Disable auto precharge BA0, BA1 Bank DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a manual PRECHARGE. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ NOP NOP t CMH Column m Bank ...
Page 62
... AH Address Row A10 Row BA0, BA1 Bank DQ t RCD t RAS t RC Notes: 1. For this example and PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ NOP NOP t CMS t CMH Column m Enable auto precharge Bank Dout Micron Technology, Inc ...
Page 63
... WRITE on bank n when registered. The precharge to bank n will begin after valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 43 on page 64). PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM READ ...
Page 64
... DQM is LOW. Figure 43: WRITE With Auto Precharge Interrupted by a WRITE Command Internal States Address Notes: 1. DQM is LOW. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK WRITE - AP NOP NOP Bank n Bank n Page active WRITE with burst of 4 ...
Page 65
... Address Row Column Enable auto precharge A10 Row BA0, BA1 Bank RCD t RAS t RC Notes: 1. For this example PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM WRITE NOP NOP NOP t CMH Bank Din m Din Din Din ...
Page 66
... Row Disable auto precharge BA0, BA1 Bank RCD t RAS t RC Notes: 1. For this example and the WRITE burst is followed by a manual PRECHARGE. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM WRITE NOP NOP NOP t CMH Bank ...
Page 67
... Address Row Enable auto precharge Row A10 BA0, BA1 Bank DQ t RCD t RAS t RC Notes: 1. For this example PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM WRITE NOP NOP t CMH Column m Bank Din Timing Diagrams T5 T6 ...
Page 68
... AUTO REFRESH The AUTO REFRESH command is used during normal operation of the SDRAM to refresh the contents of the SDRAM array. This command is non persistent must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum is generated by the internal refresh controller. This makes the address bits “ ...
Page 69
... Back-to-back AUTO REFRESH commands are not required. Self Refresh The self refresh mode can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is disabled (LOW). After the SELF REFRESH command is regis- tered, all the inputs to the SDRAM become “ ...
Page 70
... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for required for the completion of any internal refresh in progress ...
Page 71
... High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode Notes: 1. Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM t CKS), (see Figure 50 ...
Page 72
... Figure 51: Clock Suspend During WRITE Burst Internal clock Command Address Notes: 1. For this example greater, and DQM is LOW. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK CKE NOP WRITE Bank, Col n Din ...
Page 73
... Figure 52: Clock Suspend During READ Burst Internal clock Command Address Notes: 1. For this example greater, and DQM is LOW. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM CLK CKE READ NOP NOP Bank, Col n Dout Timing Diagrams ...
Page 74
... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM ...
Page 75
... Figure 47: “Single WRITE Without Auto Precharge,” on page 68: Updated figure. Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08 • Added three-quarter drive strength content. PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN 128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice RAS lock-out. ...