MT48H8M16LFB4-75 IT:J TR Micron Technology Inc, MT48H8M16LFB4-75 IT:J TR Datasheet - Page 69

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 48:
Self Refresh
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
Command
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
High-Z
Precharge all
Auto Refresh Mode
active banks
t CKS
t CMS
t AS
Single bank
PRECHARGE
All banks
Bank(s)
T0
Notes:
t CKH
t AH
t CMH
t CK
1. Back-to-back AUTO REFRESH commands are not required.
The self refresh mode can be used to retain data in the SDRAM, even if the rest of the
system is powered down. When in self refresh mode, the SDRAM retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except CKE is disabled (LOW). After the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE,
which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
enabling it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to
an indefinite period beyond that.
t RP
T1
NOP
T2
REFRESH
AUTO
t CH
t RFC
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
NOP
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CL
Tn + 1
REFRESH
t
AUTO
RAS and remains in self refresh mode for
t RFC
NOP
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©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams
To + 1
ACTIVE
Row
Bank
Row
Don’t Care