MT48H8M16LFB4-75 IT:J TR Micron Technology Inc, MT48H8M16LFB4-75 IT:J TR Datasheet - Page 44

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 19:
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
Random READ Accesses
Notes:
1. Each READ command can be to any bank. DQM is LOW.
Data from any READ burst can be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst can be followed immediately by data from a WRITE
command (subject to bus turnaround limitations). The WRITE burst can be initiated on
the clock edge immediately following the last (or last desired) data element from the
READ burst, provided that I/O contention can be avoided. In a given system design,
there is a possibility that the device driving the input data will go Low-Z before the
SDRAM DQ go to High-Z. In this case, at least a single-cycle delay should occur between
the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 20 on page 45 and
Figure 21 on page 46. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-
out from the READ. After the WRITE command is registered, the DQ will go to High-Z (or
remain at High-Z), regardless of the state of the DQM signal, provided the DQM was
active on the clock just prior to the WRITE command that truncated the READ
command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was
LOW during T4 then the WRITEs at T5 and T7 would be valid, while the WRITE at T6
would be invalid.
Command
Command
Address
Address
CLK
CLK
DQ
DQ
T0
T0
READ
Bank,
READ
Bank,
Col n
Col n
CL = 2
T1
T1
READ
READ
Bank,
Bank,
Col a
Col a
CL = 3
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
44
T2
T2
READ
Bank,
READ
Bank,
Col x
Col x
Dout
n
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
Bank,
Col m
READ
Bank,
Col m
Dout
Dout
a
n
T4
T4
NOP
NOP
Dout
Dout
x
a
T5
T5
NOP
NOP
Dout
Dout
m
x
©2008 Micron Technology, Inc. All rights reserved.
T6
Don’t Care
Timing Diagrams
NOP
Dout
m