CY7C4285V-10ASCT Cypress Semiconductor Corp, CY7C4285V-10ASCT Datasheet - Page 13

• Manufacturer Part Number: CY7C4285V-10ASCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4285V-10ASCT

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Notes
Document Number: 38-06012 Rev. *D
17. t
18. t
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW2
Q
D
0
0
WCLK
WCLK
RCLK
RCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
WEN
–Q
WEN
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. If the time between
–D
REN
REN
OE
EF
FF
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
[17]
CLKH
CLKH
t
t
t
A
WFF
REF
t
OE
Figure 6. Write Cycle Timing
Figure 7. Read Cycle Timing
t
t
CLK
CLK
t
SKEW2
NO OPERATION
SKEW1
SKEW2
[18]
t
t
DS
CLKL
t
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
t
OHZ
NO OPERATION
Page 13 of 24
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