CY7C4285V-10ASCT Cypress Semiconductor Corp, CY7C4285V-10ASCT Datasheet - Page 18

• Manufacturer Part Number: CY7C4285V-10ASCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4285V-10ASCT

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Notes
Document Number: 38-06012 Rev. *D
32. If a write is performed on this rising edge of the write clock, there are Full  (m1) words of the FIFO when PAF goes LOW.
33. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768m words in CY7C4275V, and 65536 m words in CY7C4285V.
34. t
and the rising edge of WCLK is less than t
SKEW3
D
WCLK
WCLK
RCLK
0
WEN
WEN
REN
PAF
–D
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
LD
17
Figure 16. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
t
CLKH
t
CLKH
FULL – M + 1 WORDS
(continued)
t
CLK
t
t
ENS
ENS
SKEW3
t
IN FIFO
DS
t
PAE OFFSET
ENS
, then PAF may not change state until the next WCLK rising edge.
Figure 17. Write Programmable Registers
t
ENH
t
CLKL
t
CLKL
t
ENH
t
DH
Note
32
PAF OFFSET
t
PAF
t
ENS
t
SKEW3
FULL– M WORDS
IN FIFO
t
[34]
ENS
PAE OFFSET
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
D
0
[33]
– D
t
ENH
11
t
PAF synch
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