PNX1700EH NXP Semiconductors, PNX1700EH Datasheet - Page 305
PNX1700EH
Manufacturer Part Number
PNX1700EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH.pdf
(832 pages)
Specifications of PNX1700EH
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Table 11: Signal and Event Monitoring Control Registers for the Timestamp Units
Table 12: Timestamp Unit Registers
Table 13: GPIO Time Counter
PNX17XX_SER_1
Preliminary data sheet
Bit
Offset 0x10,4034-> 0x060
31:10
9:2
1:0
a
Offset 0x10,40C4->0x0F0
31
30:0
Offset 0x10,40F4
31
30:0
Bit
Bit
IO_SEL cannot be written to unless timestamping is disabled (EVENT_MODE=00).
Symbol
Unused
IO_SEL
EVENT_MODE
Symbol
Direction
Timestamp
Symbol
Unused
TIME_CTR
a
4.5 Signal and Event Monitoring Control Registers for the Timestamp
4.6 Timestamp Unit Registers
4.7 GPIO Time Counter
TIME_CTR
Units
TSU<0-11>
GPIO_EV<4-15>
Acces
s
R/W
R/W
Acces
s
R
R
Acces
s
R
Value
-
0
0
Value
0
0
Value
-
0
Rev. 1 — 17 March 2006
Description
This field selects the GPIO pin or internal global signal to be
monitored. Refer to
Timestamping event mode:
Description
This field indicates the direction of the event which occurred:
This field holds the 31-bit timestamp.
Description
GPIO master time counter. This counter is incremented at a
frequency of 13.5 MHz.
00 - event detection disabled
01 - capture negative edge
10 - capture positive edge
11 - capture either edge
0 - a falling edge
1 - a rising edge
Chapter 8: General Purpose Input Output Pins
Section 4.15
for field values.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
8-34
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