PNX1700EH NXP Semiconductors, PNX1700EH Datasheet - Page 87
PNX1700EH
Manufacturer Part Number
PNX1700EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH.pdf
(832 pages)
Specifications of PNX1700EH
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
3. System Resources
Table 2: PNX17xx Series Boot Options
PNX17XX_SER_1
Preliminary data sheet
BOOT_MODE
000
100
001
101
x10
s11
other
3.1 System Reset
3.2 System Booting
Description
Set up system, and start the TM5250 CPU from a 8-bit NOR Flash or ROM attached to PCI/
XIO
Set up system, and start the TM5250 CPU from a 16-bit NOR Flash or ROM attached to PCI/
XIO
Set up system, and start the TM5250 CPU from a 8-bit NAND Flash attached to PCI/XIO
Set up system, and start the TM5250 CPU from a 16-bit NAND Flash attached to PCI/XIO
Boots in host assisted mode with a default SubSystem ID of 0x1234 and a default System
Vendor ID of 0x5678. This boot mode can be used for standalone system but should not be
used for a PC PCI plug-in card since such a board requires a personal System Vendor and
SubSystem ID. Instead the I
Boots from a I
supported. The entire system can be initialized in a custom fashion by the boot command
structure. The I
and to the main memory. BOOT_MODE[2] defines the speed of the I
kHz.
Reserved
The PNX17xx Series includes a system reset module. This reset module provides a
synchronous reset to internal PNX17xx Series logic and a reset output pin for
initialization of external system components. A system reset can be initiated in
response to a board level reset input pin, a software configuration write or as a result
of a programmable watchdog timer time-out. This watchdog timer is a fail-safe
recovery mechanism which may be enabled by software. When enabled, a periodic
interrupt is sent to the TM5250 CPU. If the CPU does not respond to the interrupt
within a programmable time-out period, then the system is assumed to be hung and
the system reset is asserted.
Boot also resets board level peripherals by asserting the SYS_RST_OUT_N pin.
The PNX17xx Series boot method is controlled by the BOOT_MODE[7:0] pins’
resistive straps. The
be found in
the code on these pins is sampled. The pins operate as GPIO pins after boot.
The PNX17xx Series on-chip TM5250 CPU is capable of direct standard Flash
execution to allow for booting. Note: Direct execution from NAND Flash, a.k.a. disk
Flash is not supported. Direct execution from flash, however, has very limited
performance. Hence, the TM5250 typically copies a Flash file to high-performance
system DRAM, and executes it in DRAM. That Flash file contains the self-
decompressing initial system software application. This multi-stage boot process that
starts a compressed code module minimizes system memory cost.
2
Chapter 6 Boot
C EEPROM attached to the I
2
C EEPROM holds write commands and writes data to internal MMIO registers
Rev. 1 — 17 March 2006
Table 2
2
C boot EEPROM should be used.
Module. At the time of the RESET_IN input deassertion,
shows the main boot modes available. More details can
2
C bus. EEPROMs of 2 KB - 64 KB size are
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
2
C bus, i.e. 100 or 400
Chapter 2: Overview
2-6
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