XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 73

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

DS610 (v3.0) October 4, 2010
Product Specification
CS484 Footprint
Left Half of Package
(Top View)
156
41
51
28
32
84
24
36
24
2
2
4
I/O:
general-purpose user I/O.
INPUT:
general-purpose input pin.
DUAL:
pins, then possible user
I/O.
VREF:
voltage reference for bank.
CLK:
clock buffer input.
CONFIG:
configuration pin
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Managem
JTAG:
port pins.
GND:
VCCO:
supply for bank.
VCCINT:
supply voltage (+1.2V).
VCCAUX:
supply voltage
Unrestricted,
User I/O, input, or
Ground.
Dedicated JTAG
User I/O or input
Configuration
Output voltage
Unrestricted,
Internal core
Dedicated
Auxiliary
s.
ent pins.
Figure 15: CS484 Package Footprint (Top View–Left Half)
www.xilinx.com
W
M
A
A
A
B
A
B
C
D
E
G
H
K
N
P
R
U
V
Y
F
J
L
T
VREF_3
VREF_3
VREF_3
VREF_3
INPUT
INPUT
LHCLK2
LHCLK3
L35N_3
INPUT
L39N_3
L02N_3
L04P_3
L04N_3
L06N_3
L11P_3
L11N_3
L14N_3
L19P_3
L19N_3
L22P_3
L22N_3
L25P_3
L28N_3
L30P_3
L30N_3
L33N_3
L35P_3
IRDY2
GND
TMS
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
PROG_
VCCAUX
VCCAUX
VCCO_3
VCCO_3
VCCO_3
VCCO_3
LHCLK5
INPUT
INPUT
VREF_2
L02P_3
L06P_3
L14P_3
L17P_3
L20N_3
L25N_3
L28P_3
L33P_3
L37N_3
L39P_3
GND
GND
GND
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
B
2
Spartan-3A DSP FPGA Family: Pinout Descriptions
INPUT
INPUT
LHCLK4
INPUT
INPUT
INPUT
INPUT
INPUT
L01N_2
L30N_0
L30P_0
L08P_3
L09P_3
L01P_3
L01N_3
L05P_3
L16P_3
L17N_3
L20P_3
L23P_3
L31P_3
L31N_3
L34P_3
L27P_3
L27N_3
L36N_3
L37P_3
L01P_2
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
M0
3
VCCAUX
VREF_3
INPUT
VREF_2
L28N_0
L28P_0
L29N_0
INPUT
L08N_3
L09N_3
L03P_3
L05N_3
INPUT
L16N_3
L13P_3
INPUT
L23N_3
L32P_3
L34N_3
L38P_3
L36P_3
L03N_2
L04N_2
L04P_2
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
2
RDWR_B
VCCAUX
VCCAUX
VCCO_2
VCCO_0
VCCO_3
VCCO_3
INPUT
LHCLK1
L25N_0
L29P_0
L03N_3
L07P_3
L10P_3
L13N_3
L15N_3
L18N_3
L24N_3
L32N_3
L29N_3
L38N_3
L03P_2
L07P_2
L05P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
LHCLK0
LHCLK6
INPUT
INPUT
L25P_0
L24P_0
L21P_0
L21N_0
INPUT
L07N_3
L10N_3
INPUT
L12P_3
L15P_3
L18P_3
L21P_3
L24P_3
L26P_3
L26N_3
L29P_3
L02P_2
L07N_2
L05N_2
TRDY2
GND
GND
VS2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
Bank 0
6
Bank 2
VCCINT
VCCINT
PUDC_B
VCCAUX
VCCAUX
VCCAUX
VREF_0
VREF_0
VREF_3
INPUT
LHCLK7
INPUT
L24N_0
L26P_0
L26N_0
L31P_0
L31N_0
L12N_3
L21N_3
L02N_2
CSO_B
L11P_2
L08P_2
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
VCCINT
VCCINT
VCCINT
VCCINT
GCLK10
GCLK11
L20N_0
L27N_0
L11N_2
L06N_2
L06P_2
L13P_2
L08N_2
L09P_2
L20P_0
L22P_0
L27P_0
L23P_0
GND
GND
GND
GND
GND
GND
VS1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_2
VCCO_0
VCCO_2
VREF_2
INPUT
L13N_2
L09N_2
L18P_0
L18N_0
L16P_0
L22N_0
L23N_0
L10N_2
GCLK6
GCLK7
GND
GND
GND
GND
GND
VS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
2
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_0
GCLK13
INPUT
INPUT
INPUT
L16N_0
INPUT
L19P_0
L14N_2
L10P_2
L15N_2
L12N_2
L12P_2
GCLK8
GND
GND
GND
GND
GND
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
D6
D7
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VREF_0
GCLK12
VREF_2
INPUT
INPUT
L15N_0
L15P_0
L19N_0
L17N_0
L14P_2
L15P_2
GCLK9
GCLK5
GND
GND
GND
GND
GND
GND
GND
GND
I/O
11
I/O
I/O
I/O
I/O
I/O
D5
2
0
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