P80C552IBA NXP Semiconductors, P80C552IBA Datasheet - Page 14

• Manufacturer Part Number: P80C552IBA
• Description: MCU 8-Bit 80C 80C51 CISC ROMLess 5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P80C552IBA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 80C
• Maximum Speed: 24 MHz
• Ram Size: 256 Byte
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
4. t
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (Continued)
24 MHz version
NOTES:
2002 Sep 03
1/t
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
Serial Timing – Shift Register Mode
t
t
t
t
t
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
DW
WHQX
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
SYMBOL
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
t
CLCL
CLCL
CLCL
= 1/f
= 41.7ns at f
OSC
FIGURE
= one oscillator clock period.
3, 4
3, 4
3, 4
2
2
2
2
2
2
2
2
2
2
2
2
3
4
3
3
3
3
3
4
4
4
3
5
5
5
5
6
6
6
6
6
OSC
= 24 MHz.
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RDxs
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
Data hold after WR
RD low to address float
RD or WR high to ALE high
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
3
3
3
3
3
(Test Conditions: T
PARAMETER
amb
= 0 C to +70 C; V
1, 2
14
24 MHz CLOCK
MIN
150
150
162
283
0.5
43
17
17
17
80
75
92
12
17
17
17
17
23
0
0
0
SS
= 0 V; Load Capacitance = 80 pF)
MAX
102
128
118
183
210
175
283
65
17
10
55
67
0
5
5
10t
6t
6t
7t
2t
3t
3t
4t
2t
t
t
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
12t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MIN
3.5
VARIABLE CLOCK
17
17
CLCL
0
0
0
–25
–25
–25
–100
–100
–30
–130
–25
–25
–40
–45
–50
–75
–133
–60
80C552/83C552
10t
8t
9t
4t
3t
5t
5t
2t
3t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MAX
24
10
20
20
0
–25
–150
–165
+25
–65
–60
–80
–90
–28
+50
–133
Product data
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s