P80C552IBA NXP Semiconductors, P80C552IBA Datasheet - Page 15

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P80C552IBA

Manufacturer Part Number
P80C552IBA
Description
MCU 8-Bit 80C 80C51 CISC ROMLess 5V 68-Pin PLCC Tube
Manufacturer
NXP Semiconductors
Datasheet

Specifications of P80C552IBA

Package
68PLCC
Device Core
80C51
Family Name
80C
Maximum Speed
24 MHz
Ram Size
256 Byte
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
40
Interface Type
I2C/UART
On-chip Adc
8-chx10-bit
Operating Temperature
0 to 70 °C
Number Of Timers
3

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1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 s.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
4. t
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (Continued)
NOTES:
2002 Sep 03
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
2
HD;STA
LOW
HIGH
RC
FC
SU;DAT1
SU;DAT2
SU;DAT3
HD;DAT
SU;STA
SU;STO
BUF
RD
FD
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
C Interface (Refer to Figure 9)
SCL = 400 pF.
interface meets the I
CLCL
= 1/f
OSC
START condition hold time
SCL low time
SCL high time
SCL rise time
SCL fall time
Data set-up time
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
Repeated START set-up time
STOP condition set-up time
Bus free time
SDA rise time
SDA fall time
= one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < t
2
C-bus specification for bit-rates up to 100 kbit/s.
PARAMETER
CLCL
15
will be filtered out. Maximum capacitance on bus-lines SDA and
CLCL
INPUT
14 t
16 t
14 t
14 t
14 t
14 t
< 285 ns (16 MHz, 24 MHz > f
0.3 s
250ns
250ns
250ns
0.3 s
1 s
1 s
0ns
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
80C552/83C552
OSC
> 20 t
> 8 t
> 4.0 s
> 4.7 s
> 4.0 s
< 0.3 s
> 4.7 s
> 4.0 s
> 4.7 s
< 0.3 s
OUTPUT
> 8 t
> 3.5 MHz) the SI01
> 1 s
CLCL
CLCL
CLCL
2
2
– t
– t
1
1
1
3
1
1
1
3
1
FC
RD
Product data

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