5T9306NLGI Integrated Device Technology (Idt), 5T9306NLGI Datasheet - Page 12

• Manufacturer Part Number: 5T9306NLGI
• Description: Clock Driver 2-IN LVDS 28-Pin VFQFPN EP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 5T9306NLGI

• Package: 28VFQFPN EP
• Configuration: 1 x 2:1
• Input Signal Type: CML|eHSTL|HSTL|LVDS|LVEPECL|LVPECL|LVTTL
• Maximum Output Frequency: 1000 MHz
• Maximum Quiescent Current: 240 mA
• Operating Supply Voltage: 2.5 V

VFQFPN EPAD THERMAL RELEASE PATH
I
electrical performance, a land pattern must be incorporated on the Printed
Circuit Board (PCB) within the footprint of the package corresponding to the
exposed metal pad or exposed heat slug on the package, as shown in
Figure 1. The solderable area on the PCB, as defined by the solder mask,
should be at least the same size/shape as the exposed pad/slug area on the
package to maximize the thermal/electrical performance. Sufficient clearance
should be designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and
electrical grounding from the package to the board through a solder joint,
thermal vias are necessary to effectively conduct from the surface of the PCB
to the ground plane(s). The land pattern must be connected to ground
through these vias. The vias act as “heat pipes”. The number of vias (i.e.
IDT5T9306 Data Sheet
IDT5T9306 REVISION B JANUARY 31, 2011
n order to maximize both the removal of heat from the package and the
PIN PAD
F
PIN
IGURE
1. P.C.A
SOLDER
GROUND PLANE
SSEMBLY FOR
E
XPOSED
P
AD
EXPOSED HEAT SLUG
THERMAL VIA
T
HERMAL
12
R
“heat pipes”) are application specific and dependent upon the package
power dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to determine
the minimum number needed. Maximum thermal and electrical performance
is achieved when an array of vias is incorporated in the land pattern. It is
recommended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30 to
0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any
solder wicking inside the via during the soldering process which may result
in voids in solder between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids between the
exposed heat slug and the land pattern. Note: These recommendations are
to be used as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadframe Base Package, Amkor Technology.
ELEASE
P
ATH
–S
IDE
LAND PATTERN
(GROUND PAD)
V
IEW
SOLDER
(D
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
RAWING NOT TO
©2011 Integrated Device Technology, Inc.
S
CALE
PIN
)
PIN PAD