5T9306NLGI Integrated Device Technology (Idt), 5T9306NLGI Datasheet - Page 7

• Manufacturer Part Number: 5T9306NLGI
• Description: Clock Driver 2-IN LVDS 28-Pin VFQFPN EP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 5T9306NLGI

• Package: 28VFQFPN EP
• Configuration: 1 x 2:1
• Input Signal Type: CML|eHSTL|HSTL|LVDS|LVEPECL|LVPECL|LVTTL
• Maximum Output Frequency: 1000 MHz
• Maximum Quiescent Current: 240 mA
• Operating Supply Voltage: 2.5 V

NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times t
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
IDT5T9306 Data Sheet
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Skew Parameters
Propagation Delay
Output Gate Enable/Disable Delay
Power Down Timing
RMS Additive Phase Jitter
Output Rise/Fall Time
IDT5T9306 REVISION B JANUARY 31, 2011
Symbol
on any one device.
at identical V
t
t
t
PWRDN
PWRUP
t
t
SK
SK
SK
t
t
t
t
t
PGD
PLH
PHL
PGE
t
R
f
JIT
(
O
/t
(
(
PP
O
P
F
)
)
)
DD
levels and temperature.
Parameter
Same Device Output Pin-to-Pin Skew
Pulse Skew
Part-to-Part Skew
Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint
Frequency Range
Output Gate Enable Crossing V
Output Gate Disable Crossing V
PD Crossing V
Output Gate Disable Crossing V
RMS Additive Phase Jitter @ 25MHz (12kHz – 10MHz Integration Range)
RMS Additive Phase Jitter @ 125MHz (12kHz – 20MHz Integration Range)
RMS Additive Phase Jitter @ 156.25MHz (12kHz – 20MHz Integration Range)
Output Rise/Fall Time
(3)
THI
(4)
(6)
to Qn = V
(6)
, (20% - 80%)
DD
THI
, Qn = V
THI
THI
to Qn/Qn Crosspoint
to Qn/Qn Crosspoint Driven to GL Designated Level
to Qn/Qn Driven to GL Designated Level
PHL
(2)
and t
DD
PLH
of any differential output pair under identical input and output interfaces, transitions and load conditions
7
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Min.
125
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©2011 Integrated Device Technology, Inc.
(1,5)
0.541
0.159
0.185
Typ.
1.25
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—
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Max
1.75
125
300
100
100
600
3.5
3.5
25
1
GHz
Unit
μS
μS
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps