PN5120A0HN/C1 NXP Semiconductors, PN5120A0HN/C1 Datasheet - Page 42

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PN5120A0HN/C1

Manufacturer Part Number
PN5120A0HN/C1
Description
Transmission Module 40-Pin HVQFN EP T/R
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PN5120A0HN/C1

Package
40HVQFN EP
Operating Temperature
-30 to 85 °C

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NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.2.11 FelNFC1Reg
Defines the length of the FeliCa Sync bytes and the minimum length of the received
packet.
Table 66.
Table 67.
Bit
7 to 6
5 to 0
Access
Rights
Symbol
FelSyncLen Defines the length of the Sync bytes.
DataLenMin These bits define the minimum length of the accepted packet length:
FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b
Description of FelNFC1Reg bits
r/w
7
FelSyncLen
All information provided in this document is subject to legal disclaimers.
Description
Value
00
01
10
11
DataLenMin * 4 ≤ data packet length
This parameter is ignored at 106 kbit if the bit DetectSync in register
ModeReg is set to logic 0. If a received data packet is shorter than the
defined DataLenMin value, the data packet will be ignored.
Rev. 3.6 — 10 March 2011
r/w
6
111336
Sync- bytes in hex
B2 4D
00 B2 4D
00 00 B2 4D
00 00 00 B2 4D
r/w
5
r/w
4
r/w
3
DataLenMin
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
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