MT90820AP1 Zarlink, MT90820AP1 Datasheet - Page 18

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MT90820AP1

Manufacturer Part Number
MT90820AP1
Description
PB FREE LARGE DIGITAL SWITCH
Manufacturer
Zarlink
Datasheets
Input Stream
Input Stream
Input Stream
Input Stream
ST-BUS F0i
STi Stream
STi Stream
STi Stream
STi Stream
GCI F0i
+ 0.5 clock period shift
+1.0 clock period shift
+1.5 clock period shift
+2.0 clock period shift
+2.5 clock period shift
+3.0 clock period shift
+3.5 clock period shift
+4.0 clock period shift
+4.5 clock period shift
CLK
CLK
Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) & Frame Delay Bits (FD11, FD2-0)
Input Stream
Offset
Figure 4 - Examples for Input Offset Delay Timing
Bit 7
Bit 0
Bit 7
Bit 0
FD11
0
1
0
1
0
1
0
1
0
Measurement Result from
Bit 7
Bit 0
Zarlink Semiconductor Inc.
Frame Delay Bits
MT90820
Bit 7
Bit 0
FD2
0
0
0
0
0
0
0
1
1
18
FD1
0
0
0
1
1
1
1
0
0
FD0
0
1
1
0
0
1
1
0
0
denotes the 3/4 point of the bit cell
denotes the 3/4 point of the bit cell
OFn2
0
0
0
0
0
0
0
1
1
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
OFn1
Corresponding
0
0
0
1
1
1
1
0
0
Offset Bits
OFn0
0
1
1
0
0
1
1
0
0
Data Sheet
DLEn
1
0
1
0
1
0
1
0
1

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