MT90820AP1 Zarlink, MT90820AP1 Datasheet - Page 20

• Manufacturer Part Number: MT90820AP1
• Description: PB FREE LARGE DIGITAL SWITCH
• Manufacturer: Zarlink

Test Access Port (TAP)
The Test Access Port (TAP) provides access to the many test functions of the MT90820. It consists of three input
pins and one output pin. The following pins are from the TAP.
•
•
•
•
•
Instruction Register
In accordance with the IEEE 1149.1 standard, the MT90820 uses public instructions. The MT90820 JTAG Interface
contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when
the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic
functions: to select the test data register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and DO during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT90820 JTAG Interface contains two test data registers:
•
•
The MT90820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit
clocked out. All tristate enable bits are active high.
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells
concurrently with the operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to
Vdd when it is not driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is
set to a high impedance state.
Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VDD.
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90820 core logic.
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
Zarlink Semiconductor Inc.
MT90820
20
Data Sheet