MT90820AP1 Zarlink, MT90820AP1 Datasheet - Page 7

• Manufacturer Part Number: MT90820AP1
• Description: PB FREE LARGE DIGITAL SWITCH
• Manufacturer: Zarlink

MT90820
Data Sheet
Data to be output on the serial streams may come from either the data memory or connection memory. Locations in
the connection memory are associated with particular ST-BUS output channels. When a channel is due to be
transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in
connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular
channel on a serial output stream is read from the data memory or connection memory during the previous channel
time-slot. This allows enough time for memory access and parallel-to-serial conversion.
Connection and Message Modes
In the connection mode, the addresses of the input source data for all output channels are stored in the connection
memory. The connection memory is mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table
14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream.
By having several output channels connected to the same input source channel, data can be broadcasted from one
input channel to several output channels.
In message mode, the microprocessor writes data to the connection memory locations corresponding to the output
stream and channel number. The lower half (8 least significant bits) of the connection memory content is
transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame
until the data is changed by the microprocessor.
The five most significant bits of the connection memory controls the following for an output channel: message or
connection mode, constant or variable delay, enables/tristate the ST-BUS output drivers and enables/disable the
loopback function. In addition, one of these bits allows the user to control the CSTo output.
If an output channel is set to a high-impedance state through the connection memory, the ST-BUS output
will be in a high impedance state for the duration of that channel. In addition to the per-channel control, all channels
on the ST-BUS outputs can be placed in a high impedance state by either pulling the ODE input pin low or
programming the output stand by (OSB) bit in the interface mode selection register to low. This action overrides the
individual per-channel programming by the connection memory bits.
The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The
addressing of the device internal registers, data and connection memories is performed through the address input
pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control
and Control Register bits description (Table 4, Tables 6 and 7).
Serial Data Interface Timing
The master clock frequency must always be twice the data rate. The master clock (CLK) must be either at 4.096,
8.192 or 16.384 MHz for serial data rate of 2.048, 4.096 or 8.192 Mb/s respectively. The input and output stream
data rates will always be identical.
The MT90820 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the
MT90820 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90820 is in the wide frame pulse (WFP) frame
alignment mode.
In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT90820
automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS
format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising
edge of CLK, three quarters of the way into the bit cell. In GCI format, every second rising edge of the master clock
marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell,
see Figure 12.
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Zarlink Semiconductor Inc.