C8051F336-GMR Silicon Laboratories Inc, C8051F336-GMR Datasheet - Page 121

• Manufacturer Part Number: C8051F336-GMR
• Description: Microcontrollers (MCU) 16KB 10ADC 10DAC 768Ram MCU Lead Free
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F336-GMR

• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-20
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 10 bit
• Package: 20QFN
• Device Core: 8051
• Family Name: C8051F336
• Maximum Speed: 25 MHz
• Ram Size: 768 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

20.1.3. Interfacing Port I/O to 5V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than VDD and less than 5.25V. An external pull-up resistor to the higher supply
voltage is typically required for most systems.
Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150uA to flow into the Port pin when the supply voltage is between (VDD + 0.6V) and
(VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin
is minimal. Figure 20.3 shows the input current characteristics of port pins driven above VDD. The port pin
requires 150 µA peak overdrive current when its voltage reaches approximately (VDD + 0.7 V).
WEAKPUD
(Weak Pull-Up Disable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
Port I/O Overdrive Test Circuit
V
Cell
I/O
DD
PxMDIN.x
(1 for digital)
(0 for analog)
Figure 20.2. Port I/O Cell Block Diagram
Figure 20.3. Port I/O Overdrive Current
I
Vtest
+
-
V
test
Rev.1.0
I
(µA)
Vtest
Port I/O Overdrive Current vs. Voltage
-150
-10
0
VDD
GND
V
C8051F336/7/8/9
DD
V
test
V
DD
(V)
+0.7
VDD
(WEAK)
PORT
PAD
121