AD1955ARS Analog Devices Inc, AD1955ARS Datasheet - Page 13

• Manufacturer Part Number: AD1955ARS
• Description: IC DAC AUDIO MULTIBIT 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD1955ARS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16, 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 210mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• For Use With: EVAL-AD1955EBZ - BOARD EVAL FOR AD1955
• Settling Time: -

Serial Data Format in External Digital Filter Mode
In the External Digital Filter Mode, the AD1955 will accept
up to 24-bit serial, twos complement, MSB-first data from an
external digital filter, an HDCD decoder, or a general-purpose
DSP. If the External Digital Filter Mode is selected by Control
Register 0, Bits 12 and 13, Pin 2 to Pin 5 are assigned as the word
clock input (EF_WCLK, Pin 2), bit clock input (EF_BCLK,
Pin 3), left channel data input (EF_LDATA, Pin 4), and right
channel data input (EF_RDATA, Pin 5), respectively, to accept
8f
Left and right channel data should be valid on the rising edge
of EF_BCLK. The mode can be set to Left- or Right-Justified.
A burst mode BCLK can be used in Left-Justified Mode.
Serial Data Format in SACD Mode
In the SACD Mode, the AD1955 supports both normal mode
or phase modulation mode, which are selected by Control
Register 1, Bit 6. If normal mode is selected, DSD_SCLK,
DSD_LDATA, and DSD_RDATA are used to interface with
DSD decoder chip. In this mode, the DSD data is clocked in
the AD1955 using the rising edge of DSD_SCLK with a 64f
rate, 2.8224 MHz. DSD_PHASE pin should be connected LOW.
If Phase Modulation Mode is selected, the DSD_PHASE pin is
also used to interface with the DSD decoder. In this mode, a
64f
the data from the decoder. The DSD data is clocked into the
AD1955 with a 128f
The AD1955 can operate as a master or slave device. In Master
Mode, the AD1955 will output DSD_SCLK and DSD_PHASE
(if in Phase Modulation Mode) to a DSD decoder and will
support Normal Mode and Phase Modulation Mode 0. In Slave
Mode, the AD1955 will accept DSD_SCLK and DSD_PHASE
(if in Phase Modulation Mode) from a DSD decoder and sup-
ports all of the normal and phase modulation modes.
When the SACD Port is not being used, the SACD pins (Pins
6, 7, 8, and 9) should be tied to a valid logic level. Please note
that there are weak pull-ups (0.6 mA typical) on DSD_SCLK
and DSD_PHASE.
Master Clock
The AD1955 must be set to the proper sample rate and master
clock rate using Control Registers 0 and 1. The allowable master
clock frequencies for each interpolation mode are shown below.
In the External Filter Mode, the AD1955 accepts master clock
frequencies depending on the input sample rate as shown below.
REV. 0
S
S
Interpolation Mode
48 kHz (INT 8×) Mode
96 kHz (INT 4×) Mode
192 kHz (INT 2×) Mode
Input Sample Rate
8 × f
4 × f
2 × f
(48 kHz), 4f
DSD_PHASE signal is used as a reference signal to receive
S
S
S
S
(96 kHz), or 2f
S
DSD_SCLK.
64
64
•
•
S
(196 kHz) oversampled data.
96
96
Allowable Master Clock Frequencies (
Allowable Master Clock Frequencies (
128
128
•
•
•
•
External Filter Mode
192
192
•
•
PCM Mode
S
–13–
256
256
•
•
•
•
In the SACD Mode, the AD1955 accepts a 256f
768f
Mode, by default, the rising edge of DSD_SCLK should coincide
with the rising edge of MCLK. Control Register 1, Bit 2 should
be set to 1 if the rising edge of DSD_SCLK coincides with the
falling edge of MCLK. In Master Mode this bit can be used to
select the MCLK edge used to generate the DSD clock outputs.
Zero Detection
When the AD1955 detects that the audio input data is continu-
ously zero during 1024 LRCLK periods in PCM Mode or 8192
LRCLK periods in 8f
(Pin 21) or ZEROR (Pin 20) is set to active.
When the AD1955 is in SACD Mode, it will detect an SACD
mute pattern. If the input bit stream shows a mute pattern for
about 22 ms, the AD1955 will set ZEROL (Pin 21) or ZEROR
(Pin 20) to active. The outputs can be set to active high or low
using Control Register 1, Bit 8.
Reset/Power-Down
The AD1955 will be reset when the PD/RST pin is set low. The
part may be powered down using Bit 15, Control Register 0.
Audio Outputs
Active I/V converters should be used, which will hold the DAC
outputs at a constant voltage level. Passive I/V conversion should
not be used, since the DAC performance will be seriously degraded.
For best THD + N performance over temperature, a reference
voltage of 2.80 V should be used with the I/V converters. For a
lower parts count, the voltage at FILTR can be used. In this
instance, THD + N performance at high temperature can be
improved by reducing I
(linear dependence) and DNR/SNR (square-root dependence).
The AD1955 audio outputs sink a current proportional to the
input signal, superimposed on a steady bias current. The cur-
rent-to-voltage (I/V) converters used need to be able to supply
this bias current, as well as the signal current, or a resistor or
current source can be used to a positive voltage to null this
current in order to center the range of the I/V converters.
If pull-up resistors are used to bring the output of the I/V convert-
ers to 0 V for maximum headroom and THD balance, as shown
in the applications circuits, the following equation can be used:
S
384
384
Master Clock, where f
R
•
•
PULLUP
512
512
f
f
=
S
•
S
•
)
)
[
V
SUPPLY
S
External Digital Filter Mode, ZEROL
REF
768
768
•
•
, with an attendant reduction in gain
–
S
V
is nominally 44.1 kHz. In Slave
BIAS
Nominal Input
Sample Rate (kHz)
32, 44.1, 48
88.2, 96
176.4, 192
Nominal Input Sample Rate
(to External Filter) (kHz)
32, 44.1, 48
88.2, 96
176.4, 192
]
[
I
BIAS
+
(
V
BIAS
S
AD1955
, 512f
R
I V
S
/
, or
)
]