AD5382BST-3 Analog Devices Inc, AD5382BST-3 Datasheet - Page 10
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AD5382BST-3
Manufacturer Part Number
AD5382BST-3
Description
IC DAC 14BIT 32CH 3V 100-LQFP
Manufacturer
Analog Devices Inc
Datasheet
1.AD5382BSTZ-5.pdf
(40 pages)
Specifications of AD5382BST-3
Design Resources
32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012)
Settling Time
8µs
Number Of Bits
14
Data Interface
Serial, Parallel
Number Of Converters
32
Voltage Supply Source
Single Supply
Power Dissipation (max)
65mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
For Use With
EVAL-AD5382EB - BOARD EVAL FOR AD5382
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
AD5382
I
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.
Table 7.
Parameter
F
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
2
Guaranteed by design and characterization, not production tested.
See Figure 6.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
SCL’s falling edge.
C
SCL
b
3
SDA
C SERIAL INTERFACE
SCL
b
is the total capacitance, in pF, of one bus line. t
1, 2
t
9
CONDITION
START
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1C
400
t
4
b
t
MIN
4
3
, T
MAX
t
10
R
and t
t
6
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Figure 6. I
F
are measured between 0.3 DV
2
C-Compatible Serial Interface Timing Diagram
t
2
Description
SCL clock frequency
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
SCL cycle time
t
t
t
t
t
t
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
Rev. B | Page 10 of 40
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS-compatible)
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS-compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, bus free time between a stop and a start condition
, SCL low time
, SCL high time
, setup time for repeated start
, stop condition setup time
, start/repeated start condition hold time
, data setup time
, data hold time
, data hold time
t
11
t
5
DD
and 0.7 DV
IH
min of the SCL signal) in order to bridge the undefined region of
DD
.
CONDITION
REPEATED
START
t
7
t
4
t
1
MIN
to T
MAX
,
CONDITION
STOP
t
8