DSPB56371AF150 Freescale Semiconductor, DSPB56371AF150 Datasheet - Page 38

• Manufacturer Part Number: DSPB56371AF150
• Description: IC DSP 24BIT 150MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56371AF150

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 264kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 115°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 150 MIPs
• Maximum Clock Frequency: 150 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 264 KB
• Operating Supply Voltage: 1.25 V, 3.3 V
• Maximum Operating Temperature: + 115 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Stop, Mode Select, and Interrupt Timing
11
38
Note:
No.
No.
10
11
12
13
14
15
16
17
6
7
8
9
1. Measured at 50% of the input transition
2. The maximum value for PLL enabled is given for minimum V
3. The maximum value for PLL enabled is given for minimum V
4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low
Reset, Stop, Mode Select, and Interrupt Timing
EXTAL input high
(40% to 60% duty cycle)
EXTAL input low
(40% to 60% duty cycle)
EXTAL cycle time
Instruction cycle time= I
• With PLL disabled
• With PLL enabled
• With PLL disabled
• With PLL enabled
Delay from RESET assertion to all output pins at
reset value
Required RESET duration
Syn reset setup time from RESET
Syn reset de assert delay time
Mode select setup time
Mode select hold time
Minimum edge-triggered interrupt request
assertion width
Minimum edge-triggered interrupt request
deassertion width
• Power on, external clock generator, PLL
• Power on, external clock generator, PLL
• Maximum
• Minimum
• Maximum(PLL enabled)
time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower
clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time
and low time requirements are met.
disabled
enabled
3
Characteristics
1,2
Table 19. Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
2
1,2
Table 18. Clock Operation 150 and 181 MHz Values
CYC
4
= T
C
3
DSP56371 Data Sheet, Rev. 4.1
Symbol
Icyc
Eth
Etc
Etl
CO
CO
(2xT
and maximum MF.
and maximum DF.
Expression
2 x T
2 x T
2× T
2 xT
2 xT
C
T
)+T
—
3.33ns
3.33ns
6.66ns
6.66ns
6.66ns
6.66ns
C
Min
C
C
C
C
C
LOCK
150 MHz
13.0ns
100ns
100ns
200ns
Max
inf
inf
11.1
11.1
11.1
10.0
10.0
11.1
11.1
Min
5.0
—
—
5.52ns
5.52ns
5.52ns
5.52ns
2.75ns
2.75ns
Freescale Semiconductor
Min
Max
181 MHz
5.5
11
—
—
—
—
—
—
--
13.0ns
200ns
100ns
100ns
Max
inf
inf
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns