ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet
ADMCF341BR
Specifications of ADMCF341BR
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ADMCF341BR Summary of contents
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A a FEATURES 20 MHz Fixed-Point DSP Core Single-Cycle Instruction Execution (50 ns) ADSP-21xx Family Code Compatibility Independent Computational Units ALU, Multiplier/Accumulator, Barrel Shifter Multifunction Instructions Single-Cycle Context Switch Powerful Program Sequencer Zero Overhead Looping Conditional Instruction Execution 2 Independent ...
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ADMC(F)341 SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 3 Zero Offset Comparator Delay 2 ADC High Level Input Current 2 ADC Low Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double update mode) ...
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VOLTAGE REFERENCE Parameter Voltage Level (V ) REF Drift Specifications subject to change without notice. POWER-ON RESET Parameter Reset Threshold Hysteresis Reset Active Timeout Period 16 *2 CLKOUT cycles. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS Symbol Parameter V ...
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ADMC(F)341 FLASH MEMORY (ADMCF341 ONLY) Parameter Endurance Data Retention Program and Erase Operating Temperature Read Operating Temperature Specifications subject to change without notice. TIMING PARAMETERS Parameter Clock Signals Signal t is defined as 0 The ADMC(F)341 uses an ...
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TIMING PARAMETERS Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup Before SCLK Low SCS t DR/TFS/RFS Hold After SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK ...
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... SENSE1 Model Temperature Range ADMCF341BR –40°C to +85°C ADMCF341BR-REEL –40°C to +85°C 2 ADMCF341BRZ-REEL –40°C to +85°C For information on ordering ROM models, email dsp.support@analog.com or contact a local Analog Devices sales office. 1 Ranges shown represent ambient temperature Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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GENERAL DESCRIPTION The ADMC(F)341 is a low cost, single-chip, DSP-based controller suitable for permanent magnet synchronous motors, ac induction motors, and brushless dc motors. The ADMC(F)341 integrates a 20 MHz, fixed-point DSP core with a complete set of motor control ...
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ADMC(F)341 The processor contains three independent computational units: the arithmetic and logic unit (ALU), the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set ...
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PIN FUNCTION DESCRIPTION The ADMC(F)341 is available in a 28-lead SOIC package. Table I describes the pins. Table I. Pin List Pin Group No. of Input/ Name Pins Output Function RESET 1 I Processor Reset Input 1 SPORT1 2 I/O ...
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ADMC(F)341 Special Flash Registers The flash module has four nonvolatile 8-bit registers called special flash registers (SFRs) that are accessible independent of the main flash array via the flash programming utility. These registers are for general-purpose, nonvolatile storage. When erased, ...
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DSP Control Registers The DSP core has a system control register, SYSCNTL, memory-mapped at DM (0x3FFF). SPORT1 must be configured as a serial port by setting Bit 10. SPORT0 and SPORT1 are enabled by setting Bit 11 and Bit 12. ...
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ADMC(F)341 to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. This technique also permits the closed-loop controller to change the average voltage applied to the machine winding at a faster rate, allowing wider closed-loop bandwidths ...
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The PWMDT register is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum value of 0x3FF (= 1023) corre- sponds to a maximum programmed dead time of: = × × T 1023 max CK ...
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ADMC(F)341 PWMCHA PWMCHA AH 2 PWMDT AL PWMSYNC SYSSTAT (3) PWMTM Figure 7. Typical PWM Outputs of Three-Phase Timing Unit in Single Update Mode Each switching edge is moved by an equal amount (PWMDT preserve the symmetrical ...
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Effective PWM Resolution In single update mode, the same values of PWMCHA, PWMCHB, and PWMCHC are used to define the on-times in both half cycles of the PWM period result, the effective resolution of the PWM generation process ...
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ADMC(F)341 PWMCHA = PWMCHB AH 2 PWMDT PWMTM Figure 9. An Example of PWM Signals Suitable for ECM Control. PWMCHA = PWMCHB, BH/BL Are a Crossover Pair. AL, BH, CH, and CL Outputs Are Disabled. ...
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Table V. Fundamental Characteristics of PWM Generation Unit of ADMC(F)341 Parameter 16-BIT PWM TIMER Counter Resolution Edge Resolution (Single Update Mode) Edge Resolution (Double Update Mode) Programmable Dead Time Range Programmable Dead Time Increments Programmable Pulse Deletion Range Programmable Pulse ...
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ADMC(F)341 Following reset This reset and the start of the C conversion process are initiated by the PWMSYNC pulse, as shown in Figure 12. The width of the PWMSYNC pulse is controlled by ...
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TUNED I CONST DEFAULT I CONST Figure 14. Timing Capacitor Selection Analog Front End The main analog inputs of the ADMC(F)341 ( are connected to the ADC converter through three SENSE3 front end ...
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ADMC(F)341 Table VIII. Fundamental Characteristics of Auxiliary PWM Timers Parameter Resolution PWM Frequency Each analog front end has two analog inputs: voltage and cur- rent. A 2-to-1 multiplexer selects which input will be converted; the multiplexer selection is determined by ...
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In offset mode, the switching frequencies of the two signals on the AUX0 and AUX1 pins are identical and controlled by AUXTM0 in a manner similar to that previously described for independent mode. In addition, the on-times ...
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ADMC(F)341 PORTA Pin First Alternate Function (Peripheral) PORTA8 AUX0 (Auxiliary PWM Output) PORTA7 AUX1 (Auxiliary PWM Output) PORTA6 DR1 (Data Receive SPORT1) PORTA5 FL1 (Flag Out SPORT1) PORTA4 SCLK1 (Serial Clock SPORT1) PORTA3 TFS0 (Transmit Frame Sync SPORT0) PORTA2 RFS0 ...
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Interrupt Configuration The IFC and ICNTL registers of the DSP core control and configure the interrupt controller of the DSP core. The IFC register is a 16-bit register that may be used to force and/or clear any of the eight ...
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ADMC(F)341 Table XI. SPORT0 Pin Assignment in SPI Mode SPORT I/O Signal SPI Mode DT0 (Data Transmit) MOSI (Master Output/ Slave Input) DR0 MISO (Master Input/ Slave Output) TFS0 SS (Slave Select) RFS0 Unused SCLK0 SCK (Serial Clock) DSP CORE ...
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SCK CYCLE # SCK (POLARITY = 0) SCK (POLARITY = 1) SS MOSI SEE NOTE 1 MOSO SEE NOTE 2 NOTES 1. LSB OF PREVIOUSLY TRANSMITTED WORD 2. UNDEFINED Figure 20. SPI Transfer Using Clock Phase CPHA = 0 SCK ...
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ADMC(F)341 Address (hex) Name 0x2000 ADC1 0x2001 ADC2 0x2002 ADC3 0x2003 ADCAUX 0x2004 PORTA_DIR 0x2005 PORTA_DATA 0x2006 PORTA_INTEN 0x2007 PORTA_FLAG 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 ...
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Address (hex) Name 0x3FFF SYSCNTL 0x3FFE MEMWAIT 0x3FFD TPERIOD 0x3FFC TCOUNT 0x3FFB TSCALE 0x3FFA SPORT0_RX_WORDS1 0x3FF9 SPORT0_RX_WORDS0 0x3FF8 SPORT0_TX_WORDS1 0x3FF7 SPORT0_TX_WORDS0 0x3FF6 SPORT0_CTRL_REG 0x3FF5 SPORT0_SCLKDIV 0x3FF4 SPORT0_RFSDIV 0x3FF3 SPORT0_AUTOBUF_CTRL 0x3FF2 SPORT1_CTRL_REG 0x3FF1 SPORT1_SCLKDIV 0x3FF0 SPORT1_RFSDIV 0x3FEF SPORT1_AUTOBUF_CTRL BOOT MEMORY FLASH ...
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ADMC(F)341 CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are ...
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LOW-SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH-SIDE GATE CHOPPING Figure 24. Configuration of Additional PWM Registers ...
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ADMC(F)341 CLOCKOUT 1 = AUX0 0 = PWMSYNC 1 = AUX1 Default bit values are shown value is shown, the bit field is undefined ...
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Figure 26. Configuration of Additional PIO Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown ...
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ADMC(F)341 ...
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SPORT SPORT MODE MODE SELECT 1 = UART MODE SPORT SPORT SPI MODE 1 = SPI MODE 0 = STANDARD SPI CLOCK 1 = REVERSE POLARITY 0 = PHA0 SPI CLOCK 1 = ...
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ADMC(F)341 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2) 0 ...
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DISABLED SPORT0 ENABLE 1 = DISABLED 0 = DISABLED SPORT1 ENABLE 1 = ENABLED Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray ...
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ADMC(F)341 28-Lead Standard Small Outline Package [SOIC_W] Revision History Location 10/05—Data Sheet Changed from REV REV. B. Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . ...