ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet - Page 10

• Manufacturer Part Number: ADMCF341BR
• Description: IC DSP 3CH 12BIT MOT-CTRL 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Motor Controlr

Specifications of ADMCF341BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

Special Flash Registers
The flash module has four nonvolatile 8-bit registers called
special flash registers (SFRs) that are accessible independent of
the main flash array via the flash programming utility. These
registers are for general-purpose, nonvolatile storage. When
erased, the special flash registers contain all 0s. To read special
flash registers from the user program, call the read_reg routine
contained in ROM. Refer to the ADMCF34x DSP Motor
Controller Developers Reference Manual for an example.
Boot-from-Flash Code
A security feature is available in the form of a code that,
when set, causes the processor to execute the program in
flash memory at power-up or reset. In this mode, the flash
programming utility and debugger are unable to communicate
with the ADMC(F)341. Consequently, the contents of the
flash memory can be neither programmed nor read.
The boot-from-flash code may be set via the flash programming
utility, when the user’s program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user’s program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way to
clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in
the ROM. The user program must be signaled in some way to
call the necessary routine to clear the boot-from-flash code. An
example would be to detect a high level on a PIO pin during
startup initialization and then call the flash_init or auto_erase_reg
routine. The flash_init routine will erase the entire user program
in flash memory before clearing the boot-from-flash code, thus
ensuring the security of the user program. If security is not a
concern, the auto_erase_reg routine can be used to clear the
boot-from-flash code while leaving the user program intact.
Refer to the ADMCF34x DSP Motor Controller Developer’s
Reference Manual for further instructions and an example of
using the boot-from-flash code.
FLASH PROGRAM BOOT SEQUENCE
On power-up or reset, the processor begins instruction execu-
tion at address 0x0800 of internal program ROM. The ROM
monitor program that is located there checks the boot-from-flash
code. If that code is set, the processor jumps to location 0x2200
in external flash program memory, where it expects to find the
user’s application program.
If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF34x
DSP Motor Controller Developers Reference Manual.
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMC(F)341
with an external crystal.
ADMC(F)341
Figure 4. Basic System Configuration
CLKOUT
RESET
ADMC(F)341
CLKIN
XTAL
10MHz
22pF
22pF
–10–
Clock Signals
The ADMC(F)341 can be clocked either by a crystal or a TTL-
compatible clock signal. For normal operation, the CLKIN input
cannot be halted, changed during operation, or operated below the
specified minimum frequency. If an external clock is used, it should
be a TTL-compatible signal running at half the instruction rate.
The signal is connected to the CLKIN pin of the ADMC(F)341.
In this mode, with an external clock signal, the XTAL pin must be
left unconnected. The ADMC(F)341 uses an input clock with a
frequency equal to half the instruction rate; a 10 MHz input clock
yields a 50 ns processor cycle (which is equivalent to 20 MHz).
Normally, instructions are executed in a single processor cycle. All
device timing is relative to the internal instruction rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADMC(F)341 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source,
as shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins with two capacitors, as shown in
Figure 4. A parallel-resonant, fundamental frequency, micropro-
cessor grade crystal should be used. A clock output signal
(CLKOUT) is generated by the processor at the processor’s cycle
rate of twice the input frequency.
Reset
The ADMC(F)341 DSP core and peripherals must be correctly
reset when the device is powered up to ensure proper unitization.
The ADMC(F)341 contains an integrated power-on-reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMC(F)341 V
in reset while V
When this voltage is exceeded, the ADMC(F)341 is held in reset
for an additional 216 DSP clock cycles (T
this time (T
operating condition. On power-down, when the voltage on the
V
reset. Also, if the external RESET pin is actively pulled low at
any time after power-up, a complete hardware reset of the
ADMC(F)341 is initiated.
The ADMC(F)341 sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT register,
and performs a full reset of all of the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET pin low.
The RESET signal must be the minimum pulse width specification,
t
code from the internal PM ROM located at 0x0800.
RSP
DD
RESET
. Following the reset sequence, the DSP core starts executing
pin falls below V
V
V
RST
DD
RST
Figure 5. Power-On Reset Operation
), the supply voltage must reach the recommended
DD
DD
is less than the threshold voltage level, V
pin and holds the DSP core and peripherals
RST
–V
T
HYST
RST
, the ADMC(F)341 will be
RST
in Figure 5). During
V
RST –
V
HYST
REV. B
RST
.