ADMCF341BR Analog Devices Inc, ADMCF341BR Datasheet - Page 12

• Manufacturer Part Number: ADMCF341BR
• Description: IC DSP 3CH 12BIT MOT-CTRL 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Motor Controlr

Specifications of ADMCF341BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters. This technique
also permits the closed-loop controller to change the average
voltage applied to the machine winding at a faster rate, allowing
wider closed-loop bandwidths to be achieved. The operating mode
of the PWM block (single or double update mode) is selected by
a control bit in the MODECTRL register.
The PWM generator of the ADMC(F)341 also provides an
internal signal that synchronizes the PWM switching frequency
to the A/D operation. In single update mode, a PWMSYNC
pulse is produced at the start of each PWM period. In double
update mode, an additional PWMSYNC pulse is produced at
the midpoint of each PWM period. The width of the PWMSYNC
pulse is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMC(F)341 can be shut
off in a number of different ways. First, there is a dedicated
asynchronous PWM shutdown pin, PWMTRIP, that, when
brought LOW, instantaneously places all six PWM outputs in
the OFF state. In addition, PWM shutdown is initiated when
the voltage on any of the input pins (I
thresholds (high or low) or the input is unconnected (floating).
Because these two hardware shutdown mechanisms are asyn-
chronous, and the associated PWM disable circuitry does not
use clocked logic, the PWM will shut down even if the DSP
clock is not running. The PWM system may also be shut down
from software by writing to the PWMSWT register.
Status information about the PWM system of the ADMC(F)341
is available to the user in the SYSSTAT register. In particular,
the state of PWMTRIP is available, as well as a status bit that
indicates whether the operation is in the first half or the second
half of the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener-
ating two interrupts to the DSP core. One interrupt is generated
on the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulse width modulated
signals with high resolution and minimal processor overhead.
There are four main configuration registers (PWMTM,
ADMC(F)341
• The three-phase PWM timing unit, which is the core of the
• The output control unit allows the redirection of the outputs
• The GATE drive unit provides the high chopping frequency
• The PWM shutdown controller manages the three PWM
PWM controller, generates three pairs of complemented
and dead-time-adjusted center-based PWM signals.
of the three-phase timing unit for each channel to either the
high-side or the low-side output. In addition, the output
control unit allows individual enabling/disabling of each of
the six PWM output signals.
and its subsequent mixing with the PWM signals.
shutdown modes (via the PWMTRIP pin, the analog block,
or the PWMSWT register) and generates the correct
RESET signal for the timing unit.
SENSE
) exceeds the trip
–12–
PWMDT, PWMPD, and PWMSYNCWT) that determine the
fundamental characteristics of the PWM outputs. In addition,
the operating mode of the PWM (single or double update
mode) is selected by Bit 6 of the MODECTRL register. These
registers, in conjunction with the three 16-bit duty cycle reg-
isters (PWMCHA, PWMCHB, and PWMCHC), control the
output of the three-phase timing unit.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is t
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of t
required PWMTM value is a function of the desired PWM
switching frequency (f
Therefore, the PWM switching period, T
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
to load into the PWMTM register is:
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
for a CLKOUT frequency of 20 MHz.
PWM Switching Dead Time: PWMDT Register
The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (e.g., AH) and
turning on its complementary signal (e.g., AL). This short time
delay is introduced to permit the power switch being turned off
to completely recover its blocking capability before the comple-
mentary switch is turned on. This time delay prevents a potentially
destructive short-circuit condition from developing across the
dc link capacitor of a typical voltage source inverter.
Dead time is controlled by the PWMDT register. The dead time
is inserted into the three pairs of PWM output signals. The dead
time, T
Therefore, a PWMDT value of 0x00A (= 10) introduces a
1 µs delay between the turn-off of any PWM signal (e.g., AH)
and the turn-on of its complementary signal (e.g., AL). The
amount of the dead time can therefore be programmed in incre-
ments of 2 t
D
, is related to the value in the PWMDT register by:
PWMTM
T
CK
CK
D
PWMTM
clock increments in half a PWM period. The
=
(or 100 ns for a 20 MHz CLKOUT).
f
PWMDT
PWM,min
T
S
PWM
=
CK
=
2 10 10
=
2
) and is given by:
20 10
×
=
= 1/f
×
2 65 535
× ×
2
20 10
PWMTM
×
×
2
f
CLKOUT
×
×
CLKOUT
×
f
t
6
,
PWM
S
CK
= 100 µs), the correct value
3
6
=
= ×
1000 0 3 8
, where f
×
2
=
=
t
S
153
CK
, can be written as:
f
CLKINT
f
PWMDT
PWM
f
=
CLKOUT
Hz
CLKOUT
x E
is the
REV. B