AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 13

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

MULTIPROCESSOR BUS REQUEST AND HOST BUS REQUEST
Use these specifications for passing of the bus mastership among multiprocessing ADSP-2106xs ( BR x) or a host processor ( HBR , HBG ).
Table 12. Specifications
Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
1
2
3
4
HBGRCSV
SHBRI
HHBRI
SHBGI
HHBGI
SBRI
HBRI
SRPBAI
HRPBAI
DHBGO
HHBGO
DBRO
HBRO
DCPAO
TRCPA
DRDYCS
TRDYHG
ARDYTR
For first asynchronous access after HBR and CS asserted, ADDR
easily accomplished by driving an upper address signal high when HBG is asserted.
Required only for recognition in the current cycle.
CPA assertion must meet the setup to CLKIN; de-assertion does not need to meet the setup to CLKIN.
(O/D) = open drain; (A/D) = active drive.
HBG Low to RD/WR/CS Valid
HBR Setup before CLKIN
HBR Hold before CLKIN
HBG Setup before CLKIN
HBG Hold before CLKIN High
BRx, CPA Setup before CLKIN
BRx, CPA Hold before CLKIN High
RPBA Setup before CLKIN
RPBA Hold before CLKIN
HBG Delay after CLKIN
HBG Hold after CLKIN
BRx Delay after CLKIN
BRx Hold after CLKIN
CPA Low Delay after CLKIN
CPA Disable after CLKIN
REDY (O/D) or (A/D) Low from CS and HBR Low
REDY (O/D) Disable or REDY (A/D) High from HBG
REDY (A/D) Disable from CS or HBR High
2
2
1
3
4
31–0
must be a non-MMS value 1/2 t
4
4
Rev. B | Page 13 of 48
Min
20 + 3 DT/4
13 + DT/2
13 + DT/2
21 + 3 DT/4
−2 − DT/8
−2 − DT/8
–2 − DT/8
40 + 27 DT/16
5 V
CK
Max
19.5 + 5 DT/4
13.5 + 3 DT/4
5.5 + DT/2
5.5 + DT/2
11.5 + 3 DT/4
8 − DT/8
8 − DT/8
9 − DT/8
+5.5 − DT/8
9.5
11
before RD or WR goes low, or by t
Min
20 + 3 DT/4
13 + DT/2
13 + DT/2
21 + 3 DT/4
−2 − DT/8
−2 − DT/8
−2 − DT/8
40 + 27 DT/16
AD14060/AD14060L
HBGRCSV
3.3 V
after HBG goes low. This is
Max
19.5 + 5 DT/4
13.5 + 3 DT/4
5.5 + DT/2
5.5 + DT/2
11.5 + 3 DT/4
8 − DT/8
8 − DT/8
9.5 − DT/8
+5.5 − DT/8
12
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns