AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 43

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

The load capacitance should include the processor’s package
capacitance (C
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2 t
can switch every cycle at a frequency of 1/t
at 1/(2 t
Example
Estimate P
one bank of external data memory RAM (32-bit);
four 128k × 8 RAM chips are used, each with a load of 10 pF;
external data memory writes occur every other cycle; a rate of
1/(4 t
cycle rate is 40 MHz (t
The P
drive, as shown in Table 25.A typical power consumption can
now be calculated for these conditions by adding a typical
internal power dissipation:
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all 1s to
all 0s. It is uncommon for an application to have 100% or even
50% of the outputs switching simultaneously.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ΔV is dependent on the capacitive load, C
the load current, I
following equation:
Table 25. P
Pin Type
Address
MSO
WR
Data
ADRCLK
P
P
EXT
EXT
(3.3 V) = 0.207 W.
(5 V) = 0.476 W.
P
t
CK
EXT
TOTAL
DECAY
) with 50% of the pins switching; and an instruction
CK
equation is calculated for each class of pins that can
), but selects can switch on each cycle.
EXT
= P
EXT
=
with the following assumptions: a system with
EXT
IN
Calculations
C
). The switching frequency includes driving the
L
+ (I
L
I
. This decay time can be approximated by the
L
∆
Number of Pins
15
1
1
32
1
DDIN2
V
CK
= 25 ns) and V
× 5.0 V)
INT
. Maximum P
DD
% Switching
50
0
–
50
–
CK
= 5.0 V.
CK
). The write strobe
. Select pins switch
EXT
INT
are different
cannot
L
, and
Rev. B | Page 43 of 48
× C
× 55 pF
× 55 pF
× 55 pF
× 25 pF
× 15 pF
The output disable time, t
and t
interval from when the reference signal switches to when the
output voltage decays ΔV from the measured output high or
output low voltage. t
and with ΔV equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time, t
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the output enable/disable diagram (Figure 30). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
System Hold Time Calculation Example
To determine the data output hold time in a particular system,
first calculate t
be the difference between the ADSP-2106x’s output voltage and
the input threshold for the device requiring the hold time. A
typical ΔV is 0.4 V. C
and I
The hold time is t
for the write cycle).
V
V
REFERENCE
OH (MEASURED)
OL (MEASURED)
DECAY
L
SIGNAL
is the total leakage or three-state current per data line.
OUTPUT STOPS
× f
× 20 MHz
× 20 MHz
× 40 MHz
× 20 MHz
× 40 MHz
, as shown in Figure 30. The time t
t
DRIVING
DIS
DECAY
DECAY
Figure 30. Output Enable/Disable
using the previous equation. Choose ΔV to
DECAY
L
t
V
V
MEASURED
is the total bus capacitance per data line,
OH (MEASURED)
OL (MEASURED)
plus the minimum disable time (t
t
DECAY
is calculated with test loads C
DIS
× V
× 25 V
× 25 V
× 25 V
× 25 V
× 25 V
, is the difference between t
DD
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
2
ENA
+ ∆V
– ∆V
AD14060/AD14060L
, is the interval from when a
2.0V
1.0V
MEASURED
OUTPUT STARTS
DRIVING
t
ENA
= P
= 0.206 W
= 0.00 W
= 0.055 W
= 0.200 W
= 0.015 W
V
V
EXT
OH (MEASURED)
OL (MEASURED)
is the
MEASURED
L
and I
HDWD
L
,