ADSP-2196MBST-140 Analog Devices Inc, ADSP-2196MBST-140 Datasheet - Page 34

• Manufacturer Part Number: ADSP-2196MBST-140
• Description: IC DSP CONTROLLER 16BIT 144LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2196MBST-140

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 140MHz
• Non-volatile Memory: ROM (48 kB)
• On-chip Ram: 40kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 140MHz
• Mips: 140
• Device Input Clock Speed: 140MHz
• Ram Size: 40KB
• Program Memory Size: 48KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-2196
Host Port ALE Mode Write Cycle Timing
Table 14
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description
Table 14. Host Port ALE Mode Write Cycle Timing
1
34
t
the same time.
Parameter
Switching Characteristics
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
t
t
NH
WHKS
WHKH
WHS
WHH
CSAL
ALPW
ALCSW
WCSW
ALW
WCS
HKWD
AALS
ALAH
DWS
WDH
are peripheral bus latencies (n t
and
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Figure 17
Description
HWR asserted to HACK asserted (setup, ACK Mode)
HWR de-asserted to HACK de-asserted (hold, ACK Mode)
HWR asserted to HACK asserted (setup, Ready Mode)
HWR asserted to HACK de-asserted (hold, Ready Mode)
HCMS or HCIOMS asserted to HALE asserted
HALE asserted pulsewidth
HALE de-asserted to HCMS or HCIOMS de-asserted
HWR de-asserted to HCMS or HCIOMS de-asserted
HALE de-asserted to HWR asserted
HWR de-asserted (after last byte) to HCMS or
HCIOMS de-asserted (ready for next write)
HACK asserted to HWR de-asserted (hold, ACK Mode)
Address valid to HALE de-asserted (setup)
HALE de-asserted to address invalid (hold)
Data valid to HWR de-asserted (setup)
HWR de-asserted to data invalid (hold)
describe host port write operations in Address Latch Enable (ALE) mode. For more information
HCLK
For current information contact Analog Devices at 800/262-5643
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
Min
0.6
0
4
1
1
1
1
1.5
4
1.5
4
1
on page
10.
September 2001
Max
0.6+t
2
0.6
2+t
NH
NH
1
1
REV. PrA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns