EP2C5F256C6N Altera, EP2C5F256C6N Datasheet - Page 152

• Manufacturer Part Number: EP2C5F256C6N
• Description: IC CYCLONE II FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5F256C6N

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 158
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 4608
• # I/os (max): 158
• Frequency (max): 500MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 4608
• Ram Bits: 119808
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2131

Timing Specifications
5–62
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) For extended temperature devices, the maximum output jitter (peak to peak) is 600 ps.
(11) For extended temperature devices, the maximum t
(12) For extended temperature devices, the maximum lock time is 500 us.
t
t
F A L L
L O C K
Table 5–50. LVDS Transmitter Timing Specification (Part 2 of 2)
Symbol
The maximum data rate that complies with duty cycle distortion of 45–55%.
The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with 45–55%
duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45–55% range, you
may use the higher data rate values from this column. You can calculate the duty cycle distortion as a percentage
using the absolute ps value. For example, for a data rate of 640 Mbps (UI = 1562.5 ps) and a t
duty cycle distortion is ± t
distortion of 42–58%.
The TCCS specification applies to the entire bank of LVDS, as long as the SERDES logic is placed within the LAB
adjacent to the output pins.
For extended temperature devices, the maximum input clock frequency for ×10 through ×2 modes is 137.5 MHz.
For extended temperature devices, the maximum data rate for ×10 through ×2 modes is 275 Mbps.
For extended temperature devices, the maximum input clock frequency for ×10 through ×2 modes is 200 MHz.
For extended temperature devices, the maximum data rate for ×10 through ×2 modes is 400 Mbps.
For extended temperature devices, the maximum input clock frequency for ×1 mode is 340 MHz.
For extended temperature devices, the maximum data rate for ×1 mode is 340 Mbps.
Table
Conditions
80–20%
—
5–50:
Min
150
—
–6 Speed Grade
D U T Y
Typ
200
—
/(UI*2) *100% = ± 250 ps/(1562.5 *2) * 100% = ± 8%, which gives you a duty cycle
Max
(1)
250
100
Max
(2)
Min
150
—
R I S E
–7 Speed Grade
and t
Typ
200
—
FA L L
Max
(1)
are 300 ps.
250
100
Max
(2)
Min
150
—
–8 Speed Grade
Typ
200
—
Altera Corporation
D U T Y
Max
(1)
250
100
February 2008
of 250 ps, the
(11)
(12)
Max
(2)
Unit
ps
μs