EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 102
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EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
DC Characteristics for Different Pin Types
5–12
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
Note to
(1)
Bus-hold low, sustaining
current
Bus-hold high, sustaining
current
Bus-hold low, overdrive
current
Bus-hold high, overdrive
current
Bus-hold trip point
25-Ω R
50-Ω R
50-Ω R
Table 5–11. Bus Hold Parameters
Table 5–12. Series On-Chip Termination Specifications
Symbol
There is no specification for bus-hold at V
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
For commercial –8 devices, the tolerance is ±40%.
S
S
S
Table
Parameter
Table
Internal series termination without
calibration (25-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
5–12:
5–11:
(2)
Description
Table 5–11
On-Chip Termination Specifications
Table 5–12
tolerance when using series or differential on-chip termination.
V
V
V
V
0 V < V
0 V < V
I N
I L
I N
I L
(maximum)
(minimum)
Conditions
>
<
I N
I N
—
Note (1)
< V
< V
specifies the bus hold parameters for general I/O pins.
defines the specifications for internal termination resistance
CCIO
C C I O
C C I O
V
V
V
= 1.5 V for the HSTL I/O standard.
C C I O
C C I O
C C I O
Conditions
0.68
Min
–30
30
—
—
= 3.3V
= 2.5V
= 1.8V
1.8 V
–200
Max
1.07
200
—
—
Commercial
±30
Max
±30
±30
Min
–50
0.7
(1)
50
V
—
—
CCIO
2.5 V
Resistance Tolerance
Level
Industrial
–300
Max
300
1.7
—
—
Max
±30
±30
±40
Min
–70
0.8
70
—
—
Automotive
Temp Max
Altera Corporation
Extended/
3.3 V
±40
±40
±50
February 2008
–500
Max
500
2.0
—
—
Unit
Unit
μA
μA
μA
μA
%
%
%
V