EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 61

• Manufacturer Part Number: EP2C35F672C8N
• Description: IC CYCLONE II FPGA 33K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C35F672C8N

• Number Of Logic Elements/cells: 33216
• Number Of Labs/clbs: 2076
• Total Ram Bits: 483840
• Number Of I /o: 475
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Logic Blocks: 2076
• Family Type: Cyclone II
• No. Of I/o's: 475
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1692

Altera Corporation
February 2007
Programmable Drive Strength
The output buffer for each Cyclone II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL-2 class I and II, SSTL-18 class I and II, HSTL-18 class I and II, and
HSTL-1.5 class I and II standards have several levels of drive strength that
you can control. Using minimum settings provides signal slew rate
control to reduce system noise and signal overshoot.
the possible settings for the I/O standards with drive strength control.
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL/LVCMOS (2.5 V)
LVTTL/LVCMOS (1.8 V)
Table 2–16. Programmable Drive Strength (Part 1 of 2)
I/O Standard
Top & Bottom I/O Pins
I
OH
/I
12
16
20
24
12
16
20
24
12
16
10
12
OL
Cyclone II Device Handbook, Volume 1
4
8
4
8
4
8
2
4
6
8
Current Strength Setting (mA)
Cyclone II Architecture
Table 2–16
Side I/O Pins
Note (1)
12
16
20
24
12
10
12
4
8
4
8
4
8
2
4
6
8
shows
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