EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 153
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EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2008
Notes to
(1)
(2)
(3)
(4)
(5)
f
(input clock
frequency)
HSIODR
SW
Input jitter
tolerance
t
H S C L K
L O C K
Table 5–51. LVDS Receiver Timing Specification
Symbol
For extended temperature devices, the maximum input clock frequency for x10 through x2 modes is 275 MHz.
For extended temperature devices, the maximum data rate for x10 through x2 modes is 550 Mbps.
For extended temperature devices, the maximum input clock frequency for x1 mode is 340 MHz.
For extended temperature devices, the maximum data rate for x1 mode is 340 Mbps.
For extended temperature devices, the maximum lock time is 500 us.
Table
Conditions
5–51:
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
External Memory Interface Specifications
Table 5–52
Note to
(1)
–6 Speed Grade
Table 5–52. DQS Bus Clock Skew Adder Specifications
Typ
This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×9 DQ group is 155 ps or ±77.5 ps.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table
Mode
×18
shows the DQS bus clock skew adder specifications.
×9
402.5
402.5
402.5
402.5
402.5
402.5
402.5
Max
805
805
805
805
805
300
500
100
5–52:
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
–7 Speed Grade
DQS Clock Skew Adder
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC Characteristics and Timing Specifications
402.5
402.5
155
190
Max
320
320
320
320
320
640
640
640
640
640
400
500
100
Cyclone II Device Handbook, Volume 1
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
–8 Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
402.5
402.5
320
320
320
320
320
640
640
640
640
640
100
Max
400
550
Unit
ps
ps
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(5)
(3)
(4)
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
ps
5–63