EP2C35F672C8N Altera, EP2C35F672C8N Datasheet - Page 58
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EP2C35F672C8N
Manufacturer Part Number
EP2C35F672C8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Logic Blocks
2076
Family Type
Cyclone II
No. Of I/o's
475
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1692
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure & Features
Figure 2–26. Cyclone II Device DQ & DQS Groups in ×8/×9 Mode
Notes to
(1)
(2)
2–46
Cyclone II Device Handbook, Volume 1
EP2C5
EP2C8
EP2C15
EP2C20
Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part 1 of 2)
Device
Each DQ group consists of a DQS pin, DM pin, and up to nine DQ pins.
This is an idealized pin layout. For actual pin layout, refer to the pin table.
Figure
2–26:
144-pin TQFP
208-pin PQFP
144-pin TQFP
208-pin PQFP
256-pin FineLine BGA
256-pin FineLine BGA
484-pin FineLine BGA
256-pin FineLine BGA
484-pin FineLine BGA
DQ Pins
Package
Cyclone II devices support the data strobe or read clock signal (DQS)
used in DDR and DDR2 SDRAM. Cyclone II devices can use either
bidirectional data strobes or unidirectional read clocks. The dedicated
external memory interface in Cyclone II devices also includes
programmable delay circuitry that can shift the incoming DQS signals to
center align the DQS signals within the data window.
The DQS signal is usually associated with a group of data (DQ) pins. The
phase-shifted DQS signals drive the global clock network, which is used
to clock the DQ signals on internal LE registers.
Table 2–15
(2)
(2)
®
shows the number of DQ pin groups per device.
Number of ×8
Groups
16
16
7
7
8
3
3
8
8
(3)
(3)
(3)
(4)
(4)
DQS Pin
Groups (5),
(2)
Number of ×9
3
4
3
4
4
4
8
4
8
Notes
(6)
Note (1)
(1),
DQ Pins
Number of ×16
(2)
Groups
0
3
0
3
4
4
8
4
8
Altera Corporation
Number of ×18
Groups (5),
February 2007
DM Pin
0
3
0
3
4
4
8
4
8
(6)