EP2C50F672I8N Altera, EP2C50F672I8N Datasheet - Page 50

IC CYCLONE II FPGA 50K 672-FBGA

EP2C50F672I8N

Manufacturer Part Number
EP2C50F672I8N
Description
IC CYCLONE II FPGA 50K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C50F672I8N

Number Of Logic Elements/cells
50528
Number Of Labs/clbs
3158
Total Ram Bits
594432
Number Of I /o
450
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
50528
# I/os (max)
450
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
50528
Ram Bits
594432
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2127

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I/O Structure & Features
2–38
Cyclone II Device Handbook, Volume 1
Figure 2–20. Cyclone II IOE Structure
Note to
(1)
The IOEs are located in I/O blocks around the periphery of the Cyclone II
device. There are up to five IOEs per row I/O block and up to four IOEs
per column I/O block (column I/O blocks span two columns). The row
I/O blocks drive row, column (only C4 interconnects), or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–21
Figure 2–22
There are two paths available for combinational or registered inputs to the logic
array. Each path contains a unique programmable delay chain.
Figure
Logic Array
shows how a row I/O block connects to the logic array.
shows how a column I/O block connects to the logic array.
2–20:
Input (1)
Output
OE
Output Register
Input Register
OE Register
Altera Corporation
February 2007

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