XC5VLX30T-1FFG665C Xilinx Inc, XC5VLX30T-1FFG665C Datasheet - Page 143

• Manufacturer Part Number: XC5VLX30T-1FFG665C
• Description: IC FPGA VIRTEX-5 30K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX30T-1FFG665C

• Total Ram Bits: 1327104
• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 4800
• No. Of Gates: 30000
• No. Of Macrocells: 4800
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Dc: 1045
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1560

FIFO Port Descriptions
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Figure 4-19
X-Ref Target - Figure 4-19
Table 4-15
Table 4-15: FIFO I/O Port Names and Descriptions
DI
DIP
WREN
WRCLK
RDEN
RDCLK
RESET
DO
DOP
FULL
ALMOSTFULL
EMPTY
Port Name
lists the FIFO I/O port names and descriptions.
shows the FIFO18 primitive.
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
www.xilinx.com
Figure 4-19: FIFO18 Primitive
DI[15:0]
DIP[1:0]
RDEN
RDCLK
WREN
WRCLK
RST
Write enable. When WREN = 1, data will be written to
Read enable. When RDEN = 1, data will be read to output
Asynchronous reset of all FIFO functions, flags, and
All entries in FIFO memory are filled. No additional writes
Almost all entries in FIFO memory have been filled.
Data input.
Parity-bit input.
memory. When WREN = 0, write is disabled.
Clock for write domain operation.
register. When RDEN = 0, read is disabled.
Clock for read domain operation.
pointers. RESET must be asserted for three clock cycles.
Data output, synchronous to RDCLK.
Parity-bit output, synchronous to RDCLK.
are accepted. Synchronous to WRCLK.
Synchronous to WRCLK. The offset for this flag is user
configurable. See
deassertion.
FIFO is empty. No additional reads are accepted.
Synchronous to RDCLK.
FIFO18
WRCOUNT[11:0]
ALMOSTEMPTY
RDCOUNT[11:0]
ALMOSTFULL
Table 4-16
DOP[1:0]
DO[15:0]
WRERR
RDERR
EMPTY
FULL
Description
ug190_4_15_040606
for the clock latency for flag
FIFO Port Descriptions
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