XC5VLX30T-1FFG665C Xilinx Inc, XC5VLX30T-1FFG665C Datasheet - Page 363

• Manufacturer Part Number: XC5VLX30T-1FFG665C
• Description: IC FPGA VIRTEX-5 30K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX30T-1FFG665C

• Total Ram Bits: 1327104
• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 4800
• No. Of Gates: 30000
• No. Of Macrocells: 4800
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Dc: 1045
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1560

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ISERDES Latencies
ISERDES Timing Model and Parameters
When the ISERDES interface type is MEMORY, the latency through the OCLK stage is one
CLKDIV cycle. However, the total latency through the ISERDES depends on the phase
relationship between the CLK and the OCLK clock inputs. When the ISERDES interface
type is NETWORKING, the latency is two CLKDIV cycles. See
Figure 8-13, page 369
cycle of latency in networking mode (compared to memory mode) is due to the Bitslip
submodule.
Table 8-4
characteristics in the Virtex-5 FPGA Data Sheet.
Table 8-4: ISERDES Switching Characteristics
Setup/Hold for Control Lines
T
T
T
Setup/Hold for Data Lines
T
T
Sequential Delay
T
ISCCK_BITSLIP
ISCCK_CE
ISCCK_CE
ISDCK_D
ISDCK_DDR
ISCKO_Q
describes the function and control signals of the ISERDES switching
/ T
/T
/T
/ T
Symbol
ISCKD_D
ISCKC_CE
ISCKC_CE
/ T
ISCKD_DDR
ISCKC_BITSLIP
for a visualization of latency in networking mode. The extra CLKDIV
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK (for CE1)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
D pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK at DDR mode
D pin Setup/Hold with respect to CLK at DDR mode
D pin Setup/Hold with respect to CLK at DDR mode
CLKDIV to Out at Q pins
Description
Figure 8-12, page 368
and
363