EPF8452ALC84-4 Altera, EPF8452ALC84-4 Datasheet - Page 13
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EPF8452ALC84-4
Manufacturer Part Number
EPF8452ALC84-4
Description
IC FLEX 8000A FPGA 4K 84-PLCC
Manufacturer
Altera
Series
FLEX 8000r
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8452ALC84-4
Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
68
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-PLCC
Family Name
FLEX 8000
Number Of Usable Gates
4000
Number Of Logic Blocks/elements
336
# Registers
452
# I/os (max)
68
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
336
Ram Bits
8
Device System Gates
4000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2257-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF8452ALC84-4
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EPF8452ALC84-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF8452ALC84-4N
Manufacturer:
MICROCHIP
Quantity:
1 000
Part Number:
EPF8452ALC84-4N
Manufacturer:
LATERA
Quantity:
20 000
Altera Corporation
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable signals select the signal that drives the bus.
However, if multiple output enable signals are active, contending signals
can be driven onto the bus. Conversely, if no output enable signals are
active, the bus will float. Internal tri-state emulation resolves contending
tri-state buffers to a low value and floating buses to a high value, thereby
eliminating these problems. The MAX+PLUS II software automatically
implements tri-state bus functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE is used to asynchronously load
signals into a register. The register can be set up so that LABCTRL1
implements an asynchronous load. The data to be loaded is driven to
DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register.
During compilation, the MAX+PLUS II Compiler automatically selects
the best control signal implementation. Because the clear and preset
functions are active-low, the Compiler automatically assigns a logic high
to an unused clear or preset.
The clear and preset logic is implemented in one of the following six
asynchronous modes, which are chosen during design entry. LPM
functions that use registers will automatically use the correct
asynchronous mode. See
Clear only
Preset only
Clear and preset
Load with clear
Load with preset
Load without clear or preset
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure
7.
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