EPF8452ALC84-4 Altera, EPF8452ALC84-4 Datasheet - Page 15
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EPF8452ALC84-4
Manufacturer Part Number
EPF8452ALC84-4
Description
IC FLEX 8000A FPGA 4K 84-PLCC
Manufacturer
Altera
Series
FLEX 8000r
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8452ALC84-4
Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
68
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-PLCC
Family Name
FLEX 8000
Number Of Usable Gates
4000
Number Of Logic Blocks/elements
336
# Registers
452
# I/os (max)
68
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
336
Ram Bits
8
Device System Gates
4000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2257-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF8452ALC84-4
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EPF8452ALC84-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF8452ALC84-4N
Manufacturer:
MICROCHIP
Quantity:
1 000
Part Number:
EPF8452ALC84-4N
Manufacturer:
LATERA
Quantity:
20 000
FLEX 8000 Programmable Logic Device Family Data Sheet
Asynchronous Clear
A register is cleared by one of the two LABCTRL signals. When the CLRn
port receives a low signal, the register is set to zero.
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load
or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl
asynchronously loads a 1 into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Clear & Preset
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC;
3
therefore, asserting LABCTRL1 asynchronously loads a 1 into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load with the clear, LABCTRL1
implements the asynchronous load of DATA3 by controlling the register
preset and clear. LABCTRL2 implements the clear by controlling the
register clear.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with a preset,
the MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting LABCTRL2 clears
the register, while asserting LABCTRL1 loads the register. The
MAX+PLUS II software inverts the signal that drives the DATA3 signal to
account for the inversion of the register’s output.
Asynchronous Load without Clear or Preset
When implementing an asynchronous load without the clear or preset,
LABCTRL1 implements the asynchronous load of DATA3 by controlling the
register preset and clear.
Altera Corporation
15