EPF8452ALC84-4 Altera, EPF8452ALC84-4 Datasheet - Page 16
![IC FLEX 8000A FPGA 4K 84-PLCC](/photos/6/70/67059/544-84-plcc_sml.jpg)
EPF8452ALC84-4
Manufacturer Part Number
EPF8452ALC84-4
Description
IC FLEX 8000A FPGA 4K 84-PLCC
Manufacturer
Altera
Series
FLEX 8000r
Datasheet
1.EPF8282ATC100-3.pdf
(62 pages)
Specifications of EPF8452ALC84-4
Number Of Logic Elements/cells
336
Number Of Labs/clbs
42
Number Of I /o
68
Number Of Gates
4000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-PLCC
Family Name
FLEX 8000
Number Of Usable Gates
4000
Number Of Logic Blocks/elements
336
# Registers
452
# I/os (max)
68
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
336
Ram Bits
8
Device System Gates
4000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2257-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF8452ALC84-4
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EPF8452ALC84-4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPF8452ALC84-4N
Manufacturer:
MICROCHIP
Quantity:
1 000
Part Number:
EPF8452ALC84-4N
Manufacturer:
LATERA
Quantity:
20 000
FLEX 8000 Programmable Logic Device Family Data Sheet
16
FastTrack Interconnect
In the FLEX 8000 architecture, connections between LEs and device I/O
pins are provided by the FastTrack Interconnect, a series of continuous
horizontal (row) and vertical (column) routing channels that traverse the
entire FLEX 8000 device. This device-wide routing structure provides
predictable performance even in complex designs. In contrast, the
segmented routing structure in FPGAs requires switch matrices to
connect a variable number of routing paths, which increases the delays
between logic resources and reduces performance.
The LABs within FLEX 8000 devices are arranged into a matrix of
columns and rows. Each row of LABs has a dedicated row interconnect
that routes signals both into and out of the LABs in the row. The row
interconnect can then drive I/O pins or feed other LABs in the device.
Figure 8
Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect
Note:
(1)
Row Channels
See
Table 4
shows how an LE drives the row and column interconnect.
(1)
Each LE drives one
row channel.
for the number of row channels.
LE1
LE2
to Local
Feedback
to Local
Feedback
Each LE drives up to
two column channels.
Altera Corporation
16 Column
Channels