EP2S60F484C5 Altera, EP2S60F484C5 Datasheet - Page 156

• Manufacturer Part Number: EP2S60F484C5
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484C5

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1134; EP2S60F484C5ES

Power Consumption
Power
Consumption
Timing Model
5–20
Stratix II Device Handbook, Volume 1
f
Altera
PowerPlay Early Power Estimator power calculator and the Quartus
PowerPlay Power Analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay Power Analyzer provides better
quality estimates based on the specifics of the design after place-and-
route is complete. The Power Analyzer can apply a combination of user-
entered, simulation-derived and estimated signal activities which,
combined with detailed circuit models, can yield very accurate power
estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
For more information about PowerPlay tools, refer to the PowerPlay Early
Power Estimator User Guide and the PowerPlay Early Power Estimator and
PowerPlay Power Analyzer chapters in volume 3 of the Quartus II
Handbook.
The PowerPlay Early Power Estimator is available on the Altera web site
at www.altera.com. See
specifications.
The DirectDrive
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II device densities and speed grades. This
section describes and specifies the performance, internal timing, external
timing, and PLL, high-speed I/O, external memory interface, and JTAG
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
1
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Stratix II device timing models.
®
offers two ways to calculate power for a design: the Excel-based
The timing numbers listed in the tables of this section are
extracted from the Quartus II software version 5.0 SP1.
TM
technology and MultiTrack
Table 5–4 on page 5–3
Table 5–33
TM
for typical I
shows the status of the
interconnect ensure
Altera Corporation
CC
standby
April 2011
®
II