EP2S60F484C5 Altera, EP2S60F484C5 Datasheet - Page 62

• Manufacturer Part Number: EP2S60F484C5
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484C5

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1134; EP2S60F484C5ES

PLLs & Clock Networks
2–54
Stratix II Device Handbook, Volume 1
1
Figures 2–37
clock, regional clock, and PLL external clock output, respectively.
Figure 2–37. Global Clock Control Blocks
Notes to
(1)
(2)
These clock select signals can be dynamically controlled through internal logic
when the device is operating in user mode.
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
Figure
CLKSELECT[1..0]
When using the global or regional clock control blocks in
Stratix II devices to select between multiple clocks or to enable
and disable clock networks, be aware of possible narrow pulses
or glitches when switching from one clock signal to another. A
glitch or runt pulse has a width that is less than the width of the
highest frequency input clock signal. To prevent logic errors
within the FPGA, Altera recommends that you build circuits
that filter out glitches and runt pulses.
(1)
This multiplexer supports
User-Controllable
Dynamic Switching
through
PLL Counter
2–37:
Outputs
2–39
2
2
show the clock control block for the global
CLKp
Pins
2
Enable/
Disable
GCLK
CLKn
Pin
Internal
Logic
Internal
Static Clock Select
Logic
Altera Corporation
(2)
May 2007