EP2S60F484C5 Altera, EP2S60F484C5 Datasheet - Page 184

• Manufacturer Part Number: EP2S60F484C5
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484C5

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1134; EP2S60F484C5ES

Timing Model
5–48
Stratix II Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 5–62. EP2S130 Row Pins Regional Clock Timing Parameters
Table 5–63. EP2S130 Row Pins Global Clock Timing Parameters
Table 5–64. EP2S180 Column Pins Regional Clock Timing Parameters
Parameter
Parameter
Parameter
Industrial
Industrial
Industrial
-0.113
-0.108
-0.087
-0.082
-0.307
-0.464
1.680
1.685
1.690
1.695
2.001
1.844
Minimum Timing
Minimum Timing
Minimum Timing
EP2S180 Clock Timing Parameters
Tables 5–64
for EP2S180 devices.
Commercial
Commercial
Commercial
-0.124
-0.119
-0.097
-0.092
-0.297
-0.462
1.760
1.765
1.770
1.775
2.095
1.930
through
5–67
-3 Speed
-3 Speed
-3 Speed
Grade
-0.124
Grade
-0.075
-0.079
Grade
-0.201
3.070
3.066
3.075
3.071
show the maximum clock timing parameters
3.643
3.389
0.053
-0.12
-4 Speed
-4 Speed
-4 Speed
Grade
-0.138
-0.142
Grade
-0.089
-0.093
Grade
-0.232
3.351
3.347
3.362
3.358
3.984
3.706
0.046
-5 Speed
-5 Speed
-5 Speed
Altera Corporation
Grade
-0.168
-0.173
Grade
-0.115
Grade
-0.276
3.892
3.887
3.905
3.900
4.634
4.310
0.048
-0.11
April 2011
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns