EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 300
EP2SGX60EF1152I4
Manufacturer Part Number
EP2SGX60EF1152I4
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152I4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2186
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 300 of 316
- Download datasheet (2Mb)
PLL Timing
Specifications
f
f
f
f
t
t
t
f
f
f
t
f
t
t
f
f
IN
INPFD
INDUTY
ENDUTY
INJITTER
OUTJITTER
FCOMP
OUT
OUTDUTY
SCANCLK
CONFIGEPLL
OUT_EXT
LOCK
DLOCK
SWITCHOVER
CLBW
Table 4–110. Enhanced PLL Specifications (Part 1 of 2)
Name
Input clock frequency
Input frequency to the PFD
Input clock duty cycle
External feedback input clock duty
cycle
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth
Input or external feedback clock input
jitter tolerance in terms of period jitter.
Bandwidth > 0.85 MHz
Dedicated clock output period jitter
External feedback compensation time
Output frequency for internal global or
regional clock
Duty cycle for external clock output
Scanclk frequency
Time required to reconfigure scan
chains for EPLLs
PLL external clock output frequency
Time required for the PLL to lock from
the time it is enabled or the end of
device configuration
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical clock
frequencies
Frequency range where the clock
switchover performs properly
PLL closed-loop bandwidth
Tables 4–110
operating in both the commercial junction temperature range (0 to 85 C)
and the industrial junction temperature range (–40 to 100 C), except for
the clock switchover and phase-shift stepping features. These two
features are only supported from the 0 to 100 C junction temperature
range.
≤
0.85 MHz
Description
and
4–111
describe the Stratix II GX PLL specifications when
1.5
1.5
0.13
Min
1.5
40
40
45
4
4
(2)
(2)
174/f
0.03
Typ
0.5
1.0
1.2
SCANCLK
50
1
100 MHz outclk
100 MHz outclk
25 mUI for <
250 ps for ≥
Max
16.9
500
420
550
100
500
60
60
10
55
(1)
1
1
ps or mUI
ns (peak-
ns (peak-
to-peak)
to-peak)
(p-p)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ms
ns
ns
%
%
%
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