EP2S130F1508C5N Altera, EP2S130F1508C5N Datasheet - Page 203
![IC STRATIX II FPGA 130K 1508FBGA](/photos/6/73/67335/544-stratix_ii_1508-fbga_sml.jpg)
EP2S130F1508C5N
Manufacturer Part Number
EP2S130F1508C5N
Description
IC STRATIX II FPGA 130K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F1508C5N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
1126
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1871
EP2S130F1508C5N
EP2S130F1508C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S130F1508C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
April 2011
LVTTL
2.5-V LVTTL/CMOS
1.8-V LVTTL/CMOS
1.5-V LVTTL/CMOS
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Input I/O Standard
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–77
specifies the maximum output clock toggle rates at 0pF load.
specifies the derating factors for the output clock toggle rate for a non 0pF
load.
To calculate the output toggle rate for a non 0pF load, use this formula:
The toggle rate for a non 0pF load
For example, the output toggle rate at 0pF load for SSTL-18 Class II 20mA
I/O standard is 550 MHz on a -3 device clock output pin. The derating
factor is 94ps/pF. For a 10pF load the toggle rate is calculated as:
Column I/O Pins (MHz)
500
500
500
500
500
500
500
500
500
500
500
500
-3
= 1000 / (1000/ toggle rate at 0pF load + derating factor * load value
in pF /1000)
Tables 5–77
devices.
1000 / (1000/550 + 94 × 10 /1000) = 363 (MHz)
500
500
500
500
500
500
500
500
500
500
500
500
-4
specifies the maximum input clock toggle rates.
through
450
450
450
450
450
500
500
500
500
500
500
500
-5
5–79
500
500
500
500
500
500
500
500
500
500
500
500
-3
Row I/O Pins (MHz)
show the I/O toggle rates for Stratix II
500
500
500
500
500
500
500
500
500
500
500
500
-4
Stratix II Device Handbook, Volume 1
450
450
450
450
450
500
500
500
500
500
500
500
-5
DC & Switching Characteristics
Dedicated Clock Inputs
500
500
500
500
500
500
500
500
500
500
500
500
-3
(MHz)
Table 5–78
500
500
500
500
500
500
500
500
500
500
500
500
-4
Table 5–79
400
400
400
400
400
500
500
500
500
500
500
500
-5
5–67
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